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Re: [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC |
Date: |
Thu, 7 May 2015 15:02:36 +0100 |
On 6 May 2015 at 23:50, Peter Crosthwaite <address@hidden> wrote:
> Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
> under-decoded through a 64k address region so implement aliases
> accordingly.
> + assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
> + for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
> + SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
> + const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
> + MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
> + uint32_t addr = r->address;
> + int j;
> +
> + sysbus_mmio_map(gic, r->region_index, addr);
> +
> + for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
> + MemoryRegion *alias = &s->gic_mr[i][j];
> +
> + addr += ARM_GIC_REGION_SIZE;
Since the frequency at which the GICC region repeats in the memory
map is actually board dependent, you could just use a board
specific constant here.
> + memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias",
> mr,
> + 0, ARM_GIC_REGION_SIZE);
...and here you could use memory_region_size(mr), I suppose,
or just the board-specific value again.
-- PMM
- [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 06/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 04/15] intc: arm_gic: Macroify the MemoryRegion size, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 03/15] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 02/15] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/05/06
- Re: [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC,
Peter Maydell <=
- [Qemu-devel] [PATCH target-arm v7 13/15] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 08/15] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 15/15] arm: xlnx-ep108: Add bootloading, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 11/15] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 09/15] arm: xlnx-zynqmp: Add GEM support, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 14/15] arm: xlnx-ep108: Add external RAM, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 07/15] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generalise name of A57 regs, Peter Crosthwaite, 2015/05/06