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[Qemu-devel] [PATCH 06/31] target-i386: set G=1 in SMM big real mode sel
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 06/31] target-i386: set G=1 in SMM big real mode selectors |
Date: |
Mon, 11 May 2015 15:48:52 +0200 |
Because the limit field's bits 31:20 is 1, G should be 1.
VMX actually enforces this, let's do it for completeness
in QEMU as well.
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/smm_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 6207c3a..5617a14 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -177,22 +177,22 @@ void do_smm_enter(X86CPU *cpu)
cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
}
void helper_rsm(CPUX86State *env)
--
1.8.3.1
- [Qemu-devel] [PATCH 00/31] target-i386: SMM improvements and partial support under KVM, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 01/31] pc: add 2.4 machine types, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 02/31] target-i386: introduce cpu_get_mem_attrs, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 05/31] target-i386: mask NMIs on entry to SMM, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 06/31] target-i386: set G=1 in SMM big real mode selectors,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 07/31] pflash_cfi01: change big-endian property to BIT type, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 04/31] target-i386: Use correct memory attributes for ioport accesses, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 08/31] pflash_cfi01: change to new-style MMIO accessors, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 03/31] target-i386: Use correct memory attributes for memory accesses, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 10/31] vl: allow full-blown QemuOpts syntax for -global, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 09/31] pflash_cfi01: add secure property, Paolo Bonzini, 2015/05/11