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[Qemu-devel] [PATCH 02/10] target-tricore: introduce ISA v1.6.1 feature
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 02/10] target-tricore: introduce ISA v1.6.1 feature |
Date: |
Wed, 13 May 2015 11:45:03 +0200 |
The aurix platform contains of several different cpu models and uses
the 1.6.1 ISA. This patch changes the generic aurix model to the more
specific tc27x cpu model and sets specific features.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/cpu.c | 10 +++++++---
target-tricore/cpu.h | 1 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c
index 9fe0b97..b3e5512 100644
--- a/target-tricore/cpu.c
+++ b/target-tricore/cpu.c
@@ -68,6 +68,10 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error
**errp)
CPUTriCoreState *env = &cpu->env;
/* Some features automatically imply others */
+ if (tricore_feature(env, TRICORE_FEATURE_161)) {
+ set_feature(env, TRICORE_FEATURE_16);
+ }
+
if (tricore_feature(env, TRICORE_FEATURE_16)) {
set_feature(env, TRICORE_FEATURE_131);
}
@@ -128,11 +132,11 @@ static void tc1797_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_131);
}
-static void aurix_initfn(Object *obj)
+static void tc27x_initfn(Object *obj)
{
TriCoreCPU *cpu = TRICORE_CPU(obj);
- set_feature(&cpu->env, TRICORE_FEATURE_16);
+ set_feature(&cpu->env, TRICORE_FEATURE_161);
}
typedef struct TriCoreCPUInfo {
@@ -144,7 +148,7 @@ typedef struct TriCoreCPUInfo {
static const TriCoreCPUInfo tricore_cpus[] = {
{ .name = "tc1796", .initfn = tc1796_initfn },
{ .name = "tc1797", .initfn = tc1797_initfn },
- { .name = "aurix", .initfn = aurix_initfn },
+ { .name = "tc27x", .initfn = tc27x_initfn },
{ .name = NULL }
};
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
index c14b5f9..504f156 100644
--- a/target-tricore/cpu.h
+++ b/target-tricore/cpu.h
@@ -254,6 +254,7 @@ enum tricore_features {
TRICORE_FEATURE_13,
TRICORE_FEATURE_131,
TRICORE_FEATURE_16,
+ TRICORE_FEATURE_161,
};
static inline int tricore_feature(CPUTriCoreState *env, int feature)
--
2.4.0
- [Qemu-devel] [PATCH 10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA, (continued)
- [Qemu-devel] [PATCH 10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 08/10] target-tricore: add FCALL instructions of the v1.6 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 02/10] target-tricore: introduce ISA v1.6.1 feature,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 09/10] target-tricore: add FRET instructions of the v1.6 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 06/10] target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3, Bastian Koppelmann, 2015/05/13
- [Qemu-devel] [PATCH 05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA, Bastian Koppelmann, 2015/05/13