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Re: [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA |
Date: |
Wed, 20 May 2015 10:25:40 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 |
On 05/20/2015 08:12 AM, Yongbok Kim wrote:
> +#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
> +void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, uint32_t rs,\
> + int32_t s10) \
> +{ \
> + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
> + wr_t wx; \
> + target_ulong addr = env->active_tc.gpr[rs] + (s10 << DF); \
It would be nice to clean this up a bit more. For instance, don't pass the
register number and offset. Instead, compute the address properly during
translation and pass that down.
> + int i; \
> + for (i = 0; i < DF_ELEMENTS(DF); i++) { \
> + wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
Why the varargs? They're the same all the time.
> +MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, \
> + make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
I would prefer it if you'd pass the full and proper TCGMemOp.
I.e. MO_TE | MO_{8,16,32,64} | MO_UNALN.
And you might as well hoist that out of the load/store loops.
r~