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[Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit |
Date: |
Wed, 2 Sep 2015 17:17:35 -0700 |
True, this is unused so far, but commented out is worse than
actually implemented properly.
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/int_helper.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c
index f75e1b3..6e12fab 100644
--- a/target-openrisc/int_helper.c
+++ b/target-openrisc/int_helper.c
@@ -25,19 +25,20 @@
target_ulong HELPER(ff1)(target_ulong x)
{
-/*#ifdef TARGET_OPENRISC64
- return x ? ctz64(x) + 1 : 0;
-#else*/
- return x ? ctz32(x) + 1 : 0;
-/*#endif*/
+ if (x == 0) {
+ return 0;
+ } else if (TARGET_LONG_BITS == 64) {
+ return ctz64(x) + 1;
+ } else {
+ return ctz32(x) + 1;
+ }
}
target_ulong HELPER(fl1)(target_ulong x)
{
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- return 64 - clz64(x);
-#else*/
- return 32 - clz32(x);
-/*#endif*/
+ if (TARGET_LONG_BITS == 64) {
+ return 64 - clz64(x);
+ } else {
+ return 32 - clz32(x);
+ }
}
--
2.4.3
- Re: [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE, (continued)
- [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2015/09/02