[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 |
Date: |
Thu, 08 Oct 2015 09:24:49 +0100 |
User-agent: |
mu4e 0.9.13; emacs 24.5.50.4 |
Laurent Desnogues <address@hidden> writes:
> Hello,
>
> On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias
> <address@hidden> wrote:
>> From: "Edgar E. Iglesias" <address@hidden>
>>
>> Signed-off-by: Edgar E. Iglesias <address@hidden>
>> ---
>> target-arm/cpu.h | 1 +
>> target-arm/helper.c | 12 ++++++++++++
>> 2 files changed, 13 insertions(+)
>>
>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>> index cc1578c..895f2c2 100644
>> --- a/target-arm/cpu.h
>> +++ b/target-arm/cpu.h
>> @@ -278,6 +278,7 @@ typedef struct CPUARMState {
>> };
>> uint64_t far_el[4];
>> };
>> + uint64_t hpfar_el2;
>> union { /* Translation result. */
>> struct {
>> uint64_t _unused_par_0;
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 8367997..5a5e5f0 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
>> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
>> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
>> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
>> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
>> + .type = ARM_CP_CONST, .resetvalue = 0 },
>> REGINFO_SENTINEL
>> };
>>
>> @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>> .resetvalue = 0,
>> .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
>> #endif
>> + { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
>> + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
>> + .access = PL2_RW, .accessfn = access_el3_aa32ns,
>> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
>> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
>> + .access = PL2_RW,
>> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
>> REGINFO_SENTINEL
>> };
>
> Shouldn't these last two registers be placed before the "#endif" which
> closes an "#ifndef CONFIG_USER_ONLY"?
There seem to be a bunch of _EL2 registers above the #ifndef as well so
I'm not sure it matters. In fact won't the guest just trap if it tries?
>
> Thanks,
>
> Laurent
--
Alex Bennée
- [Qemu-devel] [PATCH v3 7/9] target-arm: Add S2 translation to 32bit S1 PTWs, (continued)
- [Qemu-devel] [PATCH v3 7/9] target-arm: Add S2 translation to 32bit S1 PTWs, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v3 8/9] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2, Edgar E. Iglesias, 2015/10/08
- Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2, Alex Bennée, 2015/10/08
- Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2, Laurent Desnogues, 2015/10/09
[Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/08
Re: [Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/09
[Qemu-devel] [PATCH v3 9/9] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/08