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[Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target |
Date: |
Thu, 21 Jan 2016 14:56:25 +0000 |
The entry offset when taking an exception to AArch64 from a lower
exception level may be 0x400 or 0x600. 0x400 is used if the
implemented exception level immediately lower than the target level
is using AArch64, and 0x600 if it is using AArch32. We were
incorrectly implementing this as checking the exception level
that the exception was taken from. (The two can be different if
for example we take an exception from EL0 to AArch64 EL3; we should
in this case be checking EL2 if EL2 is implemented, and EL1 if
EL2 is not implemented.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 90c985a..06eb775 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5867,7 +5867,26 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
unsigned int new_mode = aarch64_pstate_mode(new_el, true);
if (arm_current_el(env) < new_el) {
- if (env->aarch64) {
+ /* Entry vector offset depends on whether the implemented EL
+ * immediately lower than the target level is using AArch32 or AArch64
+ */
+ bool is_aa64;
+
+ switch (new_el) {
+ case 3:
+ is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
+ break;
+ case 2:
+ is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
+ break;
+ case 1:
+ is_aa64 = is_a64(env);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (is_aa64) {
addr += 0x400;
} else {
addr += 0x600;
--
1.9.1
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target,
Peter Maydell <=
- [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init, Peter Maydell, 2016/01/21