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[Qemu-devel] [PULL 19/40] target-ppc: kvm: fix floating point registers
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 19/40] target-ppc: kvm: fix floating point registers sync on little-endian hosts |
Date: |
Mon, 1 Feb 2016 13:30:47 +1100 |
From: Greg Kurz <address@hidden>
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits
of the 32 first VSX registers. So if you have:
VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00
then
FPR31 = (uint64) 0x0102030405060708
The kernel stores the VSX registers in the fp_state struct following the
host endian element ordering.
On big-endian:
fp_state.fpr[31][0] = 0x0102030405060708
fp_state.fpr[31][1] = 0x090a0b0c0d0e0f00
On little-endian:
fp_state.fpr[31][0] = 0x090a0b0c0d0e0f00
fp_state.fpr[31][1] = 0x0102030405060708
The KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls preserve this ordering, but
QEMU considers it as big-endian and always copies element [0] to the
fpr[] array and element [1] to the vsr[] array. This does not work with
little-endian hosts, and you will get:
(qemu) p $f31
0x90a0b0c0d0e0f00
instead of:
(qemu) p $f31
0x102030405060708
This patch fixes the element ordering for little-endian hosts.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/kvm.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index c2e8912..60ff119 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -650,8 +650,13 @@ static int kvm_put_fp(CPUState *cs)
for (i = 0; i < 32; i++) {
uint64_t vsr[2];
+#ifdef HOST_WORDS_BIGENDIAN
vsr[0] = float64_val(env->fpr[i]);
vsr[1] = env->vsr[i];
+#else
+ vsr[0] = env->vsr[i];
+ vsr[1] = float64_val(env->fpr[i]);
+#endif
reg.addr = (uintptr_t) &vsr;
reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
@@ -721,10 +726,17 @@ static int kvm_get_fp(CPUState *cs)
vsx ? "VSR" : "FPR", i, strerror(errno));
return ret;
} else {
+#ifdef HOST_WORDS_BIGENDIAN
env->fpr[i] = vsr[0];
if (vsx) {
env->vsr[i] = vsr[1];
}
+#else
+ env->fpr[i] = vsr[1];
+ if (vsx) {
+ env->vsr[i] = vsr[0];
+ }
+#endif
}
}
}
--
2.5.0
- [Qemu-devel] [PULL 25/40] target-ppc: gdbstub: Add VSX support, (continued)
- [Qemu-devel] [PULL 25/40] target-ppc: gdbstub: Add VSX support, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 31/40] target-ppc: Rework ppc_store_slb, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 33/40] target-ppc: Use actual page size encodings from HPTE, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 30/40] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 24/40] target-ppc: gdbstub: fix spe registers for little-endian guests, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 38/40] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 03/40] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 10/40] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 05/40] mac_dbdma: add DBDMA controller state to VMStateDescription, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 17/40] pseries: Clean up error reporting in ppc_spapr_init(), David Gibson, 2016/01/31
- [Qemu-devel] [PULL 19/40] target-ppc: kvm: fix floating point registers sync on little-endian hosts,
David Gibson <=
- [Qemu-devel] [PULL 26/40] pseries: Allow TCG h_enter to work with hotplugged memory, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 27/40] cuda.c: return error for unknown commands, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 39/40] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro, David Gibson, 2016/01/31
- [Qemu-devel] [PULL 35/40] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(), David Gibson, 2016/01/31
- [Qemu-devel] [PULL 32/40] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/31