[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the ZynqMP IOU SLCR
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the ZynqMP IOU SLCR |
Date: |
Tue, 9 Feb 2016 14:15:15 -0800 |
Connect the I/O Unit System Level Control Registers device
to the ZynqMP model. Unfortunatly the GPIO links can not be
connected yet as the SD device is not yet attached to the
ZynqMP machine.
Signed-off-by: Alistair Francis <address@hidden>
---
V2:
- Fix up device connection
hw/arm/xlnx-zynqmp.c | 13 +++++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 1508d08..6d1b797 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -33,6 +33,8 @@
#define SATA_ADDR 0xFD0C0000
#define SATA_NUM_PORTS 2
+#define IOU_SLCR_ADDR 0xFF180000
+
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
@@ -132,6 +134,10 @@ static void xlnx_zynqmp_init(Object *obj)
TYPE_XILINX_SPIPS);
qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
}
+
+ object_initialize(&s->iou_slcr, sizeof(s->iou_slcr),
+ TYPE_XLNX_ZYNQMP_IOU_SLCR);
+ qdev_set_parent_bus(DEVICE(&s->iou_slcr), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -355,6 +361,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
&error_abort);
g_free(bus_name);
}
+
+ object_property_set_bool(OBJECT(&s->iou_slcr), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->iou_slcr), 0, IOU_SLCR_ADDR);
}
static Property xlnx_zynqmp_props[] = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 2332596..8fff0ae 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/misc/xlnx-zynqmp-iou-slcr.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/sd/sdhci.h"
@@ -81,6 +82,7 @@ typedef struct XlnxZynqMPState {
SysbusAHCIState sata;
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
+ XlnxZynqMPIOUSLCR iou_slcr;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
--
2.5.0
- [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro, (continued)
- [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 11/16] qdev: Define qdev_get_gpio_out, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 13/16] irq: Add opaque setter routine, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 12/16] qdev: Add qdev_pass_all_gpios API, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 15/16] misc: Introduce ZynqMP IOU SLCR, Alistair Francis, 2016/02/09
- [Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the ZynqMP IOU SLCR,
Alistair Francis <=
- Re: [Qemu-devel] [PATCH v4 00/16] data-driven device registers, Alex Bennée, 2016/02/26
- Re: [Qemu-devel] [PATCH v4 00/16] data-driven device registers, Alex Bennée, 2016/02/29