Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

[Peter Maydell]

On 8 February 2016 at 22:08, Jean-Christophe Dubois <address@hidden> wrote:
> For now we only support the following devices:
> * up to 4 Cortex A9 cores
> * A9 MPCORE (SCU, GIC, TWD)
> * 5 i.MX UARTs
> * 2 EPIT timers
> * 1 GPT timer
> * 3 I2C controllers
> * 7 GPIO controllers
> * 6 SDHC controllers
> * 1 CCM device
> * 1 SRC device
> * various ROM/RAM areas.
>
> Signed-off-by: Jean-Christophe Dubois <address@hidden>
> ---
>
> Changes since V1:
>  * use g_strdup_printf/g_free instead of local char array.
>  * output a message on exit for unsupported number of cores.
>
>  default-configs/arm-softmmu.mak |   1 +
>  hw/arm/Makefile.objs            |   1 +
>  hw/arm/fsl-imx6.c               | 407 ++++++++++++++++++++++++++++++++++++
>  include/hw/arm/fsl-imx6.h       | 447 
> ++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 856 insertions(+)
>  create mode 100644 hw/arm/fsl-imx6.c
>  create mode 100644 include/hw/arm/fsl-imx6.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index d9b90a5..ba3a380 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -99,6 +99,7 @@ CONFIG_ALLWINNER_A10_PIT=y
>  CONFIG_ALLWINNER_A10_PIC=y
>  CONFIG_ALLWINNER_A10=y
>
> +CONFIG_FSL_IMX6=y
>  CONFIG_FSL_IMX31=y
>  CONFIG_FSL_IMX25=y
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 2195b60..ac383df 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -15,3 +15,4 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
>  obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
>  obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
>  obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> +obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o
> diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
> new file mode 100644
> index 0000000..0faae27
> --- /dev/null
> +++ b/hw/arm/fsl-imx6.c
> @@ -0,0 +1,407 @@
> +/*
> + * Copyright (c) 2015 Jean-Christophe Dubois <address@hidden>
> + *
> + * i.MX6 SOC emulation.
> + *
> + * Based on hw/arm/fsl-imx31.c
> + *
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License as published by the
> + *  Free Software Foundation; either version 2 of the License, or
> + *  (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful, but 
> WITHOUT
> + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + *  for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/arm/fsl-imx6.h"

Include "osdep/qemu.h" first, please (see comments on patch 8).

> +#include "sysemu/sysemu.h"
> +#include "exec/address-spaces.h"
> +#include "hw/boards.h"
> +#include "sysemu/char.h"
> +#include "qemu/error-report.h"

> +static void fsl_imx6_realize(DeviceState *dev, Error **errp)
> +{
> +    FslIMX6State *s = FSL_IMX6(dev);
> +    uint16_t i;
> +    Error *err = NULL;
> +
> +    for (i = 0; i < smp_cpus; i++) {
> +
> +        if (smp_cpus == 1) {
> +            /* On uniprocessor, the CBAR is set to 0 */
> +            object_property_set_int(OBJECT(&s->cpu[i]), 0,
> +                                    "reset-cbar", &error_abort);

0 is the default for this property so you don't really need to set this.

> +        } else {
> +            object_property_set_int(OBJECT(&s->cpu[i]), 
> FSL_IMX6_A9MPCORE_ADDR,
> +                                    "reset-cbar", &error_abort);
> +        }
> +
> +        /* All CPU but CPU 0 start in power off mode */
> +        if (i) {
> +            object_property_set_bool(OBJECT(&s->cpu[i]), true,
> +                                     "start-powered-off", &error_abort);
> +        }
> +
> +        object_property_set_bool(OBJECT(&s->cpu[i]), false,
> +                                 "has_el3", &error_abort);

Do the CPUs in this board really not have EL3 ?


Otherwise this looks OK.

thanks
-- PMM