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[Qemu-devel] [PULL 04/36] target-arm: Implement MDCR_EL2.TDRA traps
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/36] target-arm: Implement MDCR_EL2.TDRA traps |
Date: |
Thu, 18 Feb 2016 14:34:36 +0000 |
Implement trapping of the "debug ROM" registers, which are controlled
by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
---
target-arm/helper.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b45d596..11eb77a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -403,6 +403,24 @@ static CPAccessResult access_tdosa(CPUARMState *env, const
ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+/* Check for traps to "debug ROM" registers, which are controlled
+ * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
+ */
+static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ int el = arm_current_el(env);
+
+ if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
+ && !arm_is_secure_below_el3(env)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ return CP_ACCESS_OK;
+}
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
@@ -3773,12 +3791,15 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
* accessor.
*/
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ .access = PL0_R, .accessfn = access_tdra,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ .access = PL1_R, .accessfn = access_tdra,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ .access = PL0_R, .accessfn = access_tdra,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
/* Monitor debug system control register; the 32-bit alias is DBGDSCRext.
*/
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
--
1.9.1
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 04/36] target-arm: Implement MDCR_EL2.TDRA traps,
Peter Maydell <=
- [Qemu-devel] [PULL 12/36] target-arm: Add the pmceid0 and pmceid1 registers, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 36/36] hw/timer: QOM'ify pxa2xx_timer, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 13/36] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 11/36] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 10/36] target-arm: Combine user-only and softmmu get/set_r13_banked(), Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 35/36] hw/timer: QOM'ify pl031, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 33/36] hw/timer: QOM'ify exynos4210_pwm, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 31/36] hw/timer: QOM'ify arm_timer (pass 2), Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 32/36] hw/timer: QOM'ify exynos4210_mct, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 29/36] hw/sd: use guest error logging rather than fprintf to stderr, Peter Maydell, 2016/02/18