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[Qemu-devel] [PATCH v6 05/10] ppc/pnv: add a XICS object to the PowerNV
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v6 05/10] ppc/pnv: add a XICS object to the PowerNV machine |
Date: |
Tue, 8 Nov 2016 09:08:05 +0100 |
Nothing more than a simple container object for the ICP and ICS. ICPs
are still created by the XICS object for the moment.
Signed-off-by: Cédric Le Goater <address@hidden>
---
David,
Please note the qdev_set_parent_bus(). That is how the reset should
be handled. I had done that before for the Aspeed SoC machine but I
had forgotten ...
hw/ppc/pnv.c | 10 ++++++++++
include/hw/ppc/pnv.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6af34241f248..435af7cf4e48 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -411,6 +411,16 @@ static void ppc_powernv_init(MachineState *machine)
}
}
+ /* Create XICS which holds all the ICPs for each thread */
+ object_initialize(&pnv->xics, sizeof(pnv->xics), TYPE_XICS_COMMON);
+ object_property_add_child(OBJECT(machine), "xics", OBJECT(&pnv->xics),
+ &error_fatal);
+ qdev_set_parent_bus(DEVICE(&pnv->xics), sysbus_get_default());
+ object_property_set_int(OBJECT(&pnv->xics), smp_cores * smp_threads,
+ "nr_servers", &error_fatal);
+ object_property_set_bool(OBJECT(&pnv->xics), true, "realized",
+ &error_fatal);
+
/* We need some cpu model to instantiate the PnvChip class */
if (machine->cpu_model == NULL) {
machine->cpu_model = "POWER8";
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 7bee658733db..cb9499728fda 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -22,6 +22,7 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/xics.h"
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
@@ -113,6 +114,8 @@ typedef struct PnvMachineState {
PnvChip **chips;
ISABus *isa_bus;
+
+ XICSState xics;
} PnvMachineState;
#define PNV_FDT_ADDR 0x01000000
--
2.7.4
- [Qemu-devel] [PATCH v6 00/10] ppc/pnv: reworking the interrupt controller, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 01/10] ppc/xics: introduce a helper to insert a new ics, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 02/10] ppc/xics: add a xics_get_cpu_index_by_pir helper, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 03/10] ppc/xics: add a 'realize' handler to the xics_common class, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 04/10] ppc/xics: add a 'set_nr_servers' handler to the xics_common class, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 05/10] ppc/pnv: add a XICS object to the PowerNV machine,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v6 06/10] ppc/pnv: add MMIO regions for ICPs, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 07/10] ppc/pnv: link the CPUs to the machine XICS, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 08/10] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 09/10] ppc/pnv: Add OCC model stub with interrupt support, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 10/10] ppc/pnv: Add Naples chip support for LPC interrupts, Cédric Le Goater, 2016/11/08