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[Qemu-devel] [PULL 10/19] target-ppc: Implement bcdcfz. instruction
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 10/19] target-ppc: Implement bcdcfz. instruction |
Date: |
Tue, 15 Nov 2016 13:48:55 +1100 |
From: Jose Ricardo Ziviani <address@hidden>
bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses
a byte to represent a digit where the most significant nibble is 0x3
or 0xf, depending on the preferred signal.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 44 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 7 ++++++
3 files changed, 52 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 180c5d0..b083c08 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -380,6 +380,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
+DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index d4106a9..2aacc94 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2787,6 +2787,50 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b,
uint32_t ps)
return cr;
}
+uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int cr = 0;
+ int invalid = 0;
+ int zone_digit = 0;
+ int zone_lead = ps ? 0xF : 0x3;
+ int digit = 0;
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+ int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4;
+
+ if (unlikely((sgnb < 0xA) && ps)) {
+ invalid = 1;
+ }
+
+ for (i = 0; i < 16; i++) {
+ zone_digit = (i * 2) ? b->u8[BCD_DIG_BYTE(i * 2)] >> 4 : zone_lead;
+ digit = b->u8[BCD_DIG_BYTE(i * 2)] & 0xF;
+ if (unlikely(zone_digit != zone_lead || digit > 0x9)) {
+ invalid = 1;
+ break;
+ }
+
+ bcd_put_digit(&ret, digit, i + 1);
+ }
+
+ if ((ps && (sgnb == 0xB || sgnb == 0xD)) ||
+ (!ps && (sgnb & 0x4))) {
+ bcd_put_digit(&ret, BCD_NEG_PREF, 0);
+ } else {
+ bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0);
+ }
+
+ cr = bcd_cmp_zero(&ret);
+
+ if (unlikely(invalid)) {
+ cr = 1 << CRF_SO;
+ }
+
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c
b/target-ppc/translate/vmx-impl.inc.c
index 795e55c..d9e3eb6 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -987,6 +987,7 @@ GEN_BCD(bcdadd)
GEN_BCD(bcdsub)
GEN_BCD2(bcdcfn)
GEN_BCD2(bcdctn)
+GEN_BCD2(bcdcfz)
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -994,6 +995,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
case 5:
gen_bcdctn(ctx);
break;
+ case 6:
+ gen_bcdcfz(ctx);
+ break;
case 7:
gen_bcdcfn(ctx);
break;
@@ -1006,6 +1010,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
static void gen_xpnd04_2(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 6:
+ gen_bcdcfz(ctx);
+ break;
case 7:
gen_bcdcfn(ctx);
break;
--
2.7.4
- [Qemu-devel] [PULL 16/19] ppc/pnv: fix xscom address translation for POWER9, (continued)
- [Qemu-devel] [PULL 16/19] ppc/pnv: fix xscom address translation for POWER9, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 06/19] ppc/pnv: fix compile breakage on old gcc, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 08/19] target-ppc: Implement bcdcfn. instruction, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 13/19] FU exceptions should carry a cause (IC), David Gibson, 2016/11/14
- [Qemu-devel] [PULL 04/19] target-ppc: add vprtyb[w/d/q] instructions, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 07/19] ppc: Remove some stub POWER6 models, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 14/19] spapr-vty: Fix bad assert() statement, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 09/19] target-ppc: Implement bcdctn. instruction, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 05/19] powernv: CPU compatibility modes don't make sense for powernv, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 17/19] ppc/pnv: Fix fatal bug on 32-bit hosts, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 10/19] target-ppc: Implement bcdcfz. instruction,
David Gibson <=
- [Qemu-devel] [PULL 11/19] target-ppc: Implement bcdctz. instruction, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 12/19] spapr: Fix migration of PCI host bridges from qemu-2.7, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 15/19] ppc/pnv: add a 'xscom_core_base' field to PnvChipClass, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 18/19] tests: add XSCOM tests for the PowerNV machine, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 19/19] boot-serial-test: Add a test for the powernv machine, David Gibson, 2016/11/14
- Re: [Qemu-devel] [PULL 00/19] ppc-for-2.8 queue 20161115, Stefan Hajnoczi, 2016/11/15