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[Qemu-devel] [PATCH 06/25] target-openrisc: Use clz and ctz opcodes
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 06/25] target-openrisc: Use clz and ctz opcodes |
Date: |
Wed, 16 Nov 2016 20:25:16 +0100 |
Cc: Jia Liu <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/helper.h | 2 --
target-openrisc/int_helper.c | 19 -------------------
target-openrisc/translate.c | 6 ++++--
3 files changed, 4 insertions(+), 23 deletions(-)
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index f53fa21..bcc7245 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -54,8 +54,6 @@ FOP_CMP(ge)
#undef FOP_CMP
/* int */
-DEF_HELPER_FLAGS_1(ff1, 0, tl, tl)
-DEF_HELPER_FLAGS_1(fl1, 0, tl, tl)
DEF_HELPER_FLAGS_3(mul32, 0, i32, env, i32, i32)
/* interrupt */
diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c
index 4d1f958..ba0fd27 100644
--- a/target-openrisc/int_helper.c
+++ b/target-openrisc/int_helper.c
@@ -24,25 +24,6 @@
#include "exception.h"
#include "qemu/host-utils.h"
-target_ulong HELPER(ff1)(target_ulong x)
-{
-/*#ifdef TARGET_OPENRISC64
- return x ? ctz64(x) + 1 : 0;
-#else*/
- return x ? ctz32(x) + 1 : 0;
-/*#endif*/
-}
-
-target_ulong HELPER(fl1)(target_ulong x)
-{
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- return 64 - clz64(x);
-#else*/
- return 32 - clz32(x);
-/*#endif*/
-}
-
uint32_t HELPER(mul32)(CPUOpenRISCState *env,
uint32_t ra, uint32_t rb)
{
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 229361a..03fa7db 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -602,11 +602,13 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
switch (op1) {
case 0x00: /* l.ff1 */
LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
+ tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1);
+ tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1);
break;
case 0x01: /* l.fl1 */
LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
+ tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS);
+ tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]);
break;
default:
--
2.7.4
- [Qemu-devel] [PATCH 00/25] tcg: Handle clz, ctz, and clrsb generically, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 02/25] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 03/25] target-cris: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 04/25] target-microblaze: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 01/25] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 05/25] target-mips: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 06/25] target-openrisc: Use clz and ctz opcodes,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/25] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 10/25] target-tricore: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 09/25] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 08/25] target-s390x: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 11/25] target-unicore32: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 12/25] target-xtensa: Use clz opcode, Richard Henderson, 2016/11/16
- [Qemu-devel] [PATCH 13/25] target-arm: Use clz opcode, Richard Henderson, 2016/11/16