[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode |
Date: |
Wed, 23 Nov 2016 14:01:30 +0100 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-s390x/helper.h | 1 -
target-s390x/int_helper.c | 6 ------
target-s390x/translate.c | 2 +-
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index 207a6e7..9102071 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -70,7 +70,6 @@ DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64,
i64)
DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64)
DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64)
DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64)
-DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i64, env, i64, i64)
diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c
index 370c94d..5bc470b 100644
--- a/target-s390x/int_helper.c
+++ b/target-s390x/int_helper.c
@@ -117,12 +117,6 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah,
uint64_t al,
return ret;
}
-/* count leading zeros, for find leftmost one */
-uint64_t HELPER(clz)(uint64_t v)
-{
- return clz64(v);
-}
-
uint64_t HELPER(cvd)(int32_t reg)
{
/* positive 0 */
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 6cebb7e..01c6217 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2249,7 +2249,7 @@ static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
/* R1 = IN ? CLZ(IN) : 64. */
- gen_helper_clz(o->out, o->in2);
+ tcg_gen_clzi_i64(o->out, o->in2, 64);
/* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
value by 64, which is undefined. But since the shift is 64 iff the
--
2.7.4
- [Qemu-devel] [PATCH v4 25/64] disas/i386.c: Handle tzcnt, (continued)
- [Qemu-devel] [PATCH v4 25/64] disas/i386.c: Handle tzcnt, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 23/64] tcg: Allow an operand to be matching or a constant, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 26/64] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 24/64] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 27/64] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 29/64] target-microblaze: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 28/64] target-cris: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 31/64] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 30/64] target-mips: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 32/64] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 34/64] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 36/64] target-unicore32: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 35/64] target-tricore: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 38/64] target-arm: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 37/64] target-xtensa: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 39/64] target-i386: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 41/64] tcg/aarch64: Handle ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 40/64] tcg/ppc: Handle ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 43/64] tcg/mips: Handle clz opcode, Richard Henderson, 2016/11/23