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[Qemu-devel] [PATCH v4 09/10] tcg-mips: Adjust calling conventions for m
From: |
Jin Guojie |
Subject: |
[Qemu-devel] [PATCH v4 09/10] tcg-mips: Adjust calling conventions for mips64 |
Date: |
Tue, 29 Nov 2016 14:07:07 +0800 |
Cc: Aurelien Jarno <address@hidden>
Cc: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Jin Guojie <address@hidden>
---
tcg/mips/tcg-target.h | 19 +++++++++++++++----
tcg/mips/tcg-target.inc.c | 21 +++++++++++++++------
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 4b7d3ae..d352c97 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -27,7 +27,14 @@
#ifndef MIPS_TCG_TARGET_H
#define MIPS_TCG_TARGET_H
-#define TCG_TARGET_REG_BITS 32
+#if _MIPS_SIM == _ABIO32
+# define TCG_TARGET_REG_BITS 32
+#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+# define TCG_TARGET_REG_BITS 64
+#else
+# error "Unknown ABI"
+#endif
+
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
#define TCG_TARGET_NB_REGS 32
@@ -71,9 +78,13 @@ typedef enum {
} TCGReg;
/* used for function call generation */
-#define TCG_TARGET_STACK_ALIGN 8
-#define TCG_TARGET_CALL_STACK_OFFSET 16
-#define TCG_TARGET_CALL_ALIGN_ARGS 1
+#define TCG_TARGET_STACK_ALIGN 16
+#if _MIPS_SIM == _ABIO32
+# define TCG_TARGET_CALL_STACK_OFFSET 16
+#else
+# define TCG_TARGET_CALL_STACK_OFFSET 0
+#endif
+#define TCG_TARGET_CALL_ALIGN_ARGS 1
/* MOVN/MOVZ instructions detection */
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 6213941..5856ef0 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -91,10 +91,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_S8,
/* Call clobbered registers. */
- TCG_REG_T0,
- TCG_REG_T1,
- TCG_REG_T2,
- TCG_REG_T3,
TCG_REG_T4,
TCG_REG_T5,
TCG_REG_T6,
@@ -105,17 +101,27 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_V0,
/* Argument registers, opposite order of allocation. */
+ TCG_REG_T3,
+ TCG_REG_T2,
+ TCG_REG_T1,
+ TCG_REG_T0,
TCG_REG_A3,
TCG_REG_A2,
TCG_REG_A1,
TCG_REG_A0,
};
-static const TCGReg tcg_target_call_iarg_regs[4] = {
+static const TCGReg tcg_target_call_iarg_regs[] = {
TCG_REG_A0,
TCG_REG_A1,
TCG_REG_A2,
- TCG_REG_A3
+ TCG_REG_A3,
+#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+#endif
};
static const TCGReg tcg_target_call_oarg_regs[2] = {
@@ -2427,6 +2433,9 @@ static void tcg_target_init(TCGContext *s)
{
tcg_target_detect_isa();
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff);
+ }
tcg_regset_set(tcg_target_call_clobber_regs,
(1 << TCG_REG_V0) |
(1 << TCG_REG_V1) |
--
2.1.0
- [Qemu-devel] [PATCH v4 00/10] tcg mips64 and mips r6 improvements, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 05/10] tcg-mips: Adjust move functions for mips64, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 02/10] tcg-mips: Add mips64 opcodes, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 04/10] tcg-mips: Add bswap32u and bswap64, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 09/10] tcg-mips: Adjust calling conventions for mips64,
Jin Guojie <=
- [Qemu-devel] [PATCH v4 06/10] tcg-mips: Adjust load/store functions for mips64, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 08/10] tcg-mips: Add tcg unwind info, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 07/10] tcg-mips: Adjust prologue for mips64, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 01/10] tcg-mips: Move bswap code to a subroutine, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 03/10] tcg-mips: Support 64-bit opcodes, Jin Guojie, 2016/11/29
- [Qemu-devel] [PATCH v4 10/10] tcg-mips: Adjust qemu_ld/st for mips64, Jin Guojie, 2016/11/29
- Re: [Qemu-devel] [PATCH v4 00/10] tcg mips64 and mips r6 improvements, no-reply, 2016/11/29