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Re: [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego |
Date: |
Wed, 22 Feb 2017 16:33:43 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 02/22/2017 08:29 PM, Nikunj A Dadhania wrote:
>> For 64-bit mode if the register RA contains 0x8000_0000_0000_0000, OV
>> and OV32 are set to 1.
>>
>> For 32-bit mode if the register RA contains 0x8000_0000, OV and OV32 are
>> set to 1.
>>
>> Use the tcg-ops for negation (neg_tl) and drop gen_op_arith_neg() as
>> nego was the last user.
>>
>> Signed-off-by: Nikunj A Dadhania <address@hidden>
>> ---
>> target/ppc/translate.c | 26 +++++++++++++++++---------
>> 1 file changed, 17 insertions(+), 9 deletions(-)
>>
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index eecdfe9..2a9f508 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -1473,14 +1473,6 @@ static void gen_subfic(DisasContext *ctx)
>> }
>>
>> /* neg neg. nego nego. */
>> -static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
>> -{
>> - TCGv zero = tcg_const_tl(0);
>> - gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],
>> cpu_gpr[rA(ctx->opcode)],
>> - zero, 0, 0, compute_ov, Rc(ctx->opcode));
>> - tcg_temp_free(zero);
>> -}
>> -
>> static void gen_neg(DisasContext *ctx)
>> {
>> tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
>> @@ -1491,7 +1483,23 @@ static void gen_neg(DisasContext *ctx)
>>
>> static void gen_nego(DisasContext *ctx)
>> {
>> - gen_op_arith_neg(ctx, 1);
>> + TCGv t0 = tcg_temp_new();
>> + TCGv zero = tcg_const_tl(0);
>> +
>> + if (NARROW_MODE(ctx)) {
>> + tcg_gen_xori_tl(t0, cpu_gpr[rA(ctx->opcode)], INT32_MIN);
>> + } else {
>> + tcg_gen_xori_tl(t0, cpu_gpr[rA(ctx->opcode)],
>> (target_ulong)INT64_MIN);
>> + }
>> +
>> + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_ov, t0, zero);
>> + tcg_gen_mov_tl(cpu_ov32, cpu_ov);
>
> I think we just now covered this is wrong in the v1 thread.
With respect to the simulator, right?
I will restore the same neg/nego behaviour using subf, as OV/OV32 will
be updated as per the simulator.
Regards
Nikunj
- Re: [Qemu-devel] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract, (continued)
- [Qemu-devel] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 02/11] target/ppc: optimize gen_write_xer(), Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 06/11] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 10/11] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 09/11] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 11/11] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/22