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Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca) |
Date: |
Fri, 24 Feb 2017 12:35:02 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 02/24/2017 01:58 PM, David Gibson wrote:
>> On Fri, Feb 24, 2017 at 06:18:22AM +0530, Nikunj A Dadhania wrote:
>>> Richard Henderson <address@hidden> writes:
>>>
>>>> On 02/24/2017 06:56 AM, Nikunj A Dadhania wrote:
>>>>> Now get rid all the split out variables so, ca, ov. After this patch,
>>>>> all the bits are stored in CPUPPCState::xer at appropriate places.
>>>>>
>>>>> Signed-off-by: Nikunj A Dadhania <address@hidden>
>>>>> ---
>>>>> target/ppc/cpu.c | 8 +---
>>>>> target/ppc/cpu.h | 26 ++++++------
>>>>> target/ppc/int_helper.c | 12 +++---
>>>>> target/ppc/translate.c | 106
>>>>> +++++++++++++++++++++++++-----------------------
>>>>> 4 files changed, 78 insertions(+), 74 deletions(-)
>>>>
>>>> I do not think this is a good direction to take this.
>>>
>>> Hmm, any particular reason?
>>
>> Right, I suggested this, but based only a suspicion that the split
>> variables weren't worth the complexity. I'm happy to be corrected by
>> someone with better knowledge of TCG, but it'd be nice to know why.
>
> Normally we're interested in minimizing the size of the generated code,
> delaying computation until we can show it being used.
>
> Now, ppc is a bit different from other targets (which might compute overflow
> for any addition insn) in that it only computes overflow when someone asks
> for
> it. Moreover, it's fairly rare for the addo/subo/nego instructions to
> be used.
> Therefore, I'm not 100% sure what the "best" solution is.
Agreed, with that logic, wont it be more efficient to move the OV/CA
updationg to respective callers, and when xer_read/write happens, its
just one tcg_ops.
> However, I'd be surprised if the least amount of code places all of
> the bits into their canonical location within XER.
>
> Do note that when looking at this, the various methods by which the OV/SO
> bits
> are copied to CR flags ought to be taken into account.
I lost you in the last two para, can you explain in detail?
Regards
Nikunj
- [Qemu-devel] [PATCH v4 11/15] target/ppc: update OV/OV32 for mull[d, w] insns, (continued)
- [Qemu-devel] [PATCH v4 11/15] target/ppc: update OV/OV32 for mull[d, w] insns, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 08/15] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 07/15] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 13/15] target/ppc: update OV/OV32 flags for add/sub, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 04/15] target/ppc: add gen_op_update_ca_legacy() helper, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Richard Henderson, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), David Gibson, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Richard Henderson, 2017/02/24
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca),
Nikunj A Dadhania <=
- Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/24
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Richard Henderson, 2017/02/24
[Qemu-devel] [PATCH v4 05/15] target/ppc: add gen_op_update_ov_legacy() helper, Nikunj A Dadhania, 2017/02/23
[Qemu-devel] [PATCH v4 14/15] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/23
[Qemu-devel] [PATCH v4 09/15] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/23
[Qemu-devel] [PATCH v4 15/15] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/23
[Qemu-devel] [PATCH v4 10/15] target/ppc: add gen_op_update_ov_isa300(), Nikunj A Dadhania, 2017/02/23
Re: [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part15, David Gibson, 2017/02/24