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[Qemu-devel] [PATCH v5 5/9] ppc/pnv: extend the machine with a XICSFabri
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v5 5/9] ppc/pnv: extend the machine with a XICSFabric interface |
Date: |
Mon, 3 Apr 2017 09:46:01 +0200 |
A XICSFabric QOM interface is used by the XICS layer to manipulate the
ICP and ICS objects. Let's define the associated handlers for the
PowerNV machine. All handlers should be defined even if there is no
ICS under the PowerNV machine yet.
Signed-off-by: Cédric Le Goater <address@hidden>
---
Changes since v4:
- removed the empty ics_get() and ics_resend() handlers
hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3fa722af82e6..2d7aa5dcfbca 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -34,6 +34,7 @@
#include "qemu/cutils.h"
#include "qapi/visitor.h"
+#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/isa/isa.h"
@@ -737,6 +738,29 @@ static const TypeInfo pnv_chip_info = {
.abstract = true,
};
+static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
+{
+ CPUState *cs;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (env->spr_cb[SPR_PIR].default_value == pir) {
+ return cpu;
+ }
+ }
+
+ return NULL;
+}
+
+static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
+{
+ PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
+
+ return cpu ? ICP(cpu->intc) : NULL;
+}
+
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -787,6 +811,7 @@ static void powernv_machine_class_props_init(ObjectClass
*oc)
static void powernv_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
mc->desc = "IBM PowerNV (Non-Virtualized)";
mc->init = ppc_powernv_init;
@@ -797,6 +822,7 @@ static void powernv_machine_class_init(ObjectClass *oc,
void *data)
mc->no_parallel = 1;
mc->default_boot_order = NULL;
mc->default_ram_size = 1 * G_BYTE;
+ xic->icp_get = pnv_icp_get;
powernv_machine_class_props_init(oc);
}
@@ -807,6 +833,10 @@ static const TypeInfo powernv_machine_info = {
.instance_size = sizeof(PnvMachineState),
.instance_init = powernv_machine_initfn,
.class_init = powernv_machine_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XICS_FABRIC },
+ { },
+ },
};
static void powernv_machine_register_types(void)
--
2.7.4
- [Qemu-devel] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 1/9] spapr: move the IRQ server number mapping under the machine, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 2/9] spapr: allocate the ICPState object from under sPAPRCPUCore, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 3/9] ppc/xics: add a realize() handler to ICPStateClass, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 5/9] ppc/pnv: extend the machine with a XICSFabric interface,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v5 4/9] ppc/pnv: add a PnvICPState object, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 6/9] ppc/pnv: extend the machine with a InterruptStatsProvider interface, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 7/9] ppc/pnv: create the ICP object under PnvCore, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 8/9] ppc/pnv: add a helper to calculate MMIO addresses registers, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 9/9] ppc/pnv: add memory regions for the ICP registers, Cédric Le Goater, 2017/04/03
- Re: [Qemu-devel] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), David Gibson, 2017/04/05