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Re: [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout |
Date: |
Mon, 10 Apr 2017 18:16:46 +1000 |
User-agent: |
Mutt/1.8.0 (2017-02-23) |
On Wed, Apr 05, 2017 at 02:41:46PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <address@hidden>
>
> This creates a legacy PCIe->PCI bridge under the PHB by default to which
> a bunch of standard devices are attached. Currently:
>
> - VGA (as specified by -vga)
> - USB (with keyboard and mouse if graphcis is enabled)
> - AHCI
> - e1000
>
> This gives us something close to a standard OpenPower platform.
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> [clg: updated for qemu-2.9
> reworked pnv_create_pci_legacy_bridge() ]
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Apart from one nit below.
> ---
> hw/ppc/pnv.c | 111
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index db6e078edcea..766e6cf4bc12 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -48,6 +48,10 @@
> #include "hw/pci/pci_bridge.h"
> #include "hw/pci/msi.h"
> #include "hw/pci-host/pnv_phb3.h"
> +#include "hw/usb.h"
> +#include "hw/ide/pci.h"
> +#include "hw/ide/ahci.h"
> +#include "net/net.h"
>
> #include <libfdt.h>
>
> @@ -573,6 +577,87 @@ static ISABus *pnv_isa_create(PnvChip *chip)
> return isa_bus;
> }
>
> +
> +/* Returns whether we want to use VGA or not */
> +static int pnv_vga_init(PCIBus *pci_bus)
> +{
> + switch (vga_interface_type) {
> + case VGA_NONE:
> + return false;
> + case VGA_DEVICE:
> + return true;
> + case VGA_STD:
> + case VGA_VIRTIO:
> + return pci_vga_init(pci_bus) != NULL;
> + default:
> + fprintf(stderr, "This vga model is not supported,"
> + "currently it only supports -vga std\n");
This message doesn't appear to be entirely accurate, since virtio-vga
is apparently supported above as well. Also this should probably be
an error_report().
> + exit(0);
> + }
> +}
> +
> +static void pnv_nic_init(PCIBus *pci_bus)
> +{
> + int i;
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> + DeviceState *dev;
> + PCIDevice *pdev;
> + Error *err = NULL;
> +
> + pdev = pci_create(pci_bus, -1, "e1000");
> + dev = &pdev->qdev;
> + qdev_set_nic_properties(dev, nd);
> + object_property_set_bool(OBJECT(dev), true, "realized", &err);
> + if (err) {
> + error_report_err(err);
> + object_unparent(OBJECT(dev));
> + exit(1);
> + }
> + }
> +}
> +
> +#define MAX_SATA_PORTS 6
> +
> +static void pnv_storage_init(PCIBus *pci_bus)
> +{
> + DriveInfo *hd[MAX_SATA_PORTS];
> + PCIDevice *ahci;
> +
> + /* Add an AHCI device. We use an ICH9 since that's all we have
> + * at hand for PCI AHCI but it shouldn't really matter
> + */
> + ahci = pci_create_simple(pci_bus, -1, "ich9-ahci");
> + g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
> + ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
> + ahci_ide_create_devs(ahci, hd);
> +}
> +
> +static PCIBus *pnv_create_pci_legacy_bridge(PnvPhb3State *phb,
> + uint8_t chassis_nr)
> +{
> + PCIDevice *dev;
> + PCIHostState *pcih = PCI_HOST_BRIDGE(phb);
> + PCIDevice *pdev;
> + PCIBus *parent;
> +
> + /* Add root complex */
> + pdev = pci_create_multifunction(pcih->bus, 0, false, TYPE_PNV_PHB3_RC);
> + qdev_prop_set_uint8(&pdev->qdev, "chassis", phb->chip_id * 4 +
> phb->phb_id);
> + qdev_prop_set_uint16(&pdev->qdev, "slot", 1);
> + qdev_init_nofail(&pdev->qdev);
> +
> + /* Setup bus for that chip */
> + parent = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
> +
> + dev = pci_create_multifunction(parent, 0, false, "pci-bridge");
> + qdev_prop_set_uint8(&dev->qdev, "chassis_nr", chassis_nr);
> + dev->qdev.id = "pci";
> + qdev_init_nofail(&dev->qdev);
> + return pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
> +}
> +
> static void ppc_powernv_init(MachineState *machine)
> {
> PnvMachineState *pnv = POWERNV_MACHINE(machine);
> @@ -581,6 +666,8 @@ static void ppc_powernv_init(MachineState *machine)
> long fw_size;
> int i;
> char *chip_typename;
> + PCIBus *pbus;
> + bool has_gfx = false;
>
> /* allocate RAM */
> if (machine->ram_size < (1 * G_BYTE)) {
> @@ -682,6 +769,30 @@ static void ppc_powernv_init(MachineState *machine)
> * host to powerdown */
> pnv->powerdown_notifier.notify = pnv_powerdown_notify;
> qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
> +
> + /* Add a PCI switch */
> + pbus = pnv_create_pci_legacy_bridge(pnv->chips[0]->phbs[0], 128);
> +
> + /* Graphics & USB */
> + if (pnv_vga_init(pbus)) {
> + has_gfx = true;
> + machine->usb |= defaults_enabled() && !machine->usb_disabled;
> + }
> + if (machine->usb) {
> + pci_create_simple(pbus, -1, "nec-usb-xhci");
> + if (has_gfx) {
> + USBBus *usb_bus = usb_bus_find(-1);
> +
> + usb_create_simple(usb_bus, "usb-kbd");
> + usb_create_simple(usb_bus, "usb-mouse");
> + }
> + }
> +
> + /* Add NIC */
> + pnv_nic_init(pbus);
> +
> + /* Add storage */
> + pnv_storage_init(pbus);
> }
>
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown, (continued)
[Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge, Cédric Le Goater, 2017/04/05