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[Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, s
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync |
Date: |
Wed, 19 Apr 2017 13:41:14 -0400 |
pmccntr_read and pmccntr_write contained duplicate code that was already
being handled by pmccntr_sync. This also moves the calls to get the
clock inside the 'if' statement so they are not executed if not needed.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 55 ++++++++++++++++-------------------------------------
1 file changed, 16 insertions(+), 39 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8888391..390256b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -973,17 +973,18 @@ static inline bool arm_ccnt_enabled(CPUARMState *env)
void pmccntr_sync(CPUARMState *env)
{
- uint64_t temp_ticks;
+ if (arm_ccnt_enabled(env) &&
+ !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) {
+ uint64_t temp_ticks;
- temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
- ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
+ temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
- temp_ticks /= 64;
- }
+ if (env->cp15.c9_pmcr & PMCRD) {
+ /* Increment once every 64 processor clock cycles */
+ temp_ticks /= 64;
+ }
- if (arm_ccnt_enabled(env)) {
env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
}
}
@@ -1007,21 +1008,11 @@ static void pmcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- uint64_t total_ticks;
-
- if (!arm_ccnt_enabled(env)) {
- /* Counter is disabled, do not change value */
- return env->cp15.c15_ccnt;
- }
-
- total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
- ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
-
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
- total_ticks /= 64;
- }
- return total_ticks - env->cp15.c15_ccnt;
+ uint64_t ret;
+ pmccntr_sync(env);
+ ret = env->cp15.c15_ccnt;
+ pmccntr_sync(env);
+ return ret;
}
static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1038,22 +1029,8 @@ static void pmselr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- uint64_t total_ticks;
-
- if (!arm_ccnt_enabled(env)) {
- /* Counter is disabled, set the absolute value */
- env->cp15.c15_ccnt = value;
- return;
- }
-
- total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
- ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
-
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
- total_ticks /= 64;
- }
- env->cp15.c15_ccnt = total_ticks - value;
+ env->cp15.c15_ccnt = value;
+ pmccntr_sync(env);
}
static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0], Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync,
Aaron Lindsay <=
- [Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 13/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2017/04/19
- [Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2017/04/19
- Re: [Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3, no-reply, 2017/04/19