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Re: [Qemu-devel] [PATCH v1 1/8] target-microblaze: Correct bit shift for
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v1 1/8] target-microblaze: Correct bit shift for the PVR0 version field |
Date: |
Tue, 20 Jun 2017 14:09:11 -0700 |
On Tue, Jun 20, 2017 at 8:51 AM, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Correct bit shift for the PVR0 version field.
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
> target/microblaze/cpu.c | 2 +-
> target/microblaze/cpu.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 3d58869..af70faa 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -182,7 +182,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error
> **errp)
> (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
> (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
> (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
> - (version_code << 16) |
> + (version_code << PVR0_VERSION_SHIFT) |
> (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK :
> 0);
>
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index bf6963b..68c33e8 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -129,6 +129,8 @@ typedef struct CPUMBState CPUMBState;
> #define PVR0_USER1_MASK 0x000000FF
> #define PVR0_SPROT_MASK 0x00000001
>
> +#define PVR0_VERSION_SHIFT 8
> +
Hey Edgar,
Where do you get 8 from?
Looking at:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug984-vivado-microblaze-ref.pdf
(page 41) 16 is correct.
Thanks,
Alistair
> /* User 2 PVR mask */
> #define PVR1_USER2_MASK 0xFFFFFFFF
>
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH v1 0/8] target-microblaze: Misc configurability, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 2/8] target-microblaze: Don't hard code 0xb as initial MB version, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 1/8] target-microblaze: Correct bit shift for the PVR0 version field, Edgar E. Iglesias, 2017/06/20
- Re: [Qemu-devel] [PATCH v1 1/8] target-microblaze: Correct bit shift for the PVR0 version field,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 3/8] target-microblaze: Add CPU versions 9.4, 9.5 and 9.6, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 5/8] target-microblaze: Introduce a use-div property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 4/8] target-microblaze: Introduce a use-barrel property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 7/8] target-microblaze: Introduce a use-msr-instr property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 6/8] target-microblaze: Introduce a use-hw-mul property, Edgar E. Iglesias, 2017/06/20