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[Qemu-devel] [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT to simd_
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 |
Date: |
Thu, 8 Feb 2018 17:31:51 +0000 |
Signed-off-by: Alex Bennée <address@hidden>
---
v2
remove superfluous helpers
---
target/arm/helper-a64.c | 13 +++++++++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 5 +++++
3 files changed, 19 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 38cdc13b3e..7952a6bfff 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -833,3 +833,16 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
}
return float16_to_uint16(a, fpst);
}
+
+/*
+ * Square Root and Reciprocal square root
+ */
+
+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+{
+ float_status *s = fpstp;
+
+ return float16_sqrt(a, s);
+}
+
+
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index d8a55142b5..905125bab1 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -81,3 +81,4 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b6cd4dd8f2..587d072d27 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10925,6 +10925,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
need_fpst = false;
break;
+ case 0x7f: /* FSQRT (vector) */
+ break;
default:
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@@ -11039,6 +11041,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
+ case 0x7f: /* FSQRT */
+ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
default:
g_assert_not_reached();
}
--
2.15.1
- Re: [Qemu-devel] [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags, (continued)
- [Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 08/32] arm/translate-a64: handle_3same_64 comment fix, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 10/32] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16,
Alex Bennée <=
- [Qemu-devel] [PATCH v2 31/32] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08