[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH] intel_iommu: allow updating FEADDR and FEUADDR
From: |
Marek Marczykowski-Górecki |
Subject: |
Re: [Qemu-devel] [PATCH] intel_iommu: allow updating FEADDR and FEUADDR with one 64bit write |
Date: |
Fri, 16 Feb 2018 22:23:01 +0100 |
User-agent: |
Mutt/1.9.1 (2017-09-22) |
On Wed, Jan 24, 2018 at 03:18:48PM +0100, Marek Marczykowski-Górecki wrote:
> Allow updating those two adjacent 32bit fields with one 64bit write.
> This fixes qemu crash when booting Xen inside.
>
> See discussion on Xen side of the thing here:
> http://xen.markmail.org/message/6mrmemrnmhxvaxba
Bump.
> Signed-off-by: Marek Marczykowski-Górecki <address@hidden>
> ---
> hw/i386/intel_iommu.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 2e841cde27..d214dce277 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2129,8 +2129,12 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
>
> /* Fault Event Address Register, 32-bit */
> case DMAR_FEADDR_REG:
> - assert(size == 4);
> - vtd_set_long(s, addr, val);
> + assert(size == 4 || size == 8);
> + if (size == 4) {
> + vtd_set_long(s, addr, val);
> + } else {
> + vtd_set_quad(s, addr, val);
> + }
> break;
>
> /* Fault Event Upper Address Register, 32-bit */
--
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
signature.asc
Description: PGP signature
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [Qemu-devel] [PATCH] intel_iommu: allow updating FEADDR and FEUADDR with one 64bit write,
Marek Marczykowski-Górecki <=