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[Qemu-devel] [PULL 19/35] target/ppc: Split out gen_st_atomic
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 19/35] target/ppc: Split out gen_st_atomic |
Date: |
Tue, 3 Jul 2018 15:57:48 +1000 |
From: Richard Henderson <address@hidden>
Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations
instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an
explicit call to gen_check_align.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 97 +++++++++++++++++++++---------------------
1 file changed, 49 insertions(+), 48 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 361b178db8..53ca8f0114 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3151,54 +3151,55 @@ static void gen_ldat(DisasContext *ctx)
}
#endif
-#define ST_ATOMIC(name, memop, tp, op) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int len = MEMOP_GET_SIZE(memop); \
- uint32_t gpr_FC = FC(ctx->opcode); \
- TCGv EA = tcg_temp_local_new(); \
- TCGv_##tp t0, t1; \
- \
- gen_addr_register(ctx, EA); \
- if (len > 1) { \
- gen_check_align(ctx, EA, len - 1); \
- } \
- t0 = tcg_temp_new_##tp(); \
- t1 = tcg_temp_new_##tp(); \
- tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
- \
- switch (gpr_FC) { \
- case 0: /* add and Store */ \
- tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
- break; \
- case 1: /* xor and Store */ \
- tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
- break; \
- case 2: /* Or and Store */ \
- tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
- break; \
- case 3: /* 'and' and Store */ \
- tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
- break; \
- case 4: /* Store max unsigned */ \
- case 5: /* Store max signed */ \
- case 6: /* Store min unsigned */ \
- case 7: /* Store min signed */ \
- case 24: /* Store twin */ \
- gen_invalid(ctx); \
- break; \
- default: \
- /* invoke data storage error handler */ \
- gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
- } \
- tcg_temp_free_##tp(t0); \
- tcg_temp_free_##tp(t1); \
- tcg_temp_free(EA); \
-}
-
-ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
-#if defined(TARGET_PPC64)
-ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
+static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
+{
+ uint32_t gpr_FC = FC(ctx->opcode);
+ TCGv EA = tcg_temp_new();
+ TCGv src, discard;
+
+ gen_addr_register(ctx, EA);
+ src = cpu_gpr[rD(ctx->opcode)];
+ discard = tcg_temp_new();
+
+ memop |= MO_ALIGN;
+ switch (gpr_FC) {
+ case 0: /* add and Store */
+ tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ break;
+ case 1: /* xor and Store */
+ tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ break;
+ case 2: /* Or and Store */
+ tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ break;
+ case 3: /* 'and' and Store */
+ tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ break;
+ case 4: /* Store max unsigned */
+ case 5: /* Store max signed */
+ case 6: /* Store min unsigned */
+ case 7: /* Store min signed */
+ case 24: /* Store twin */
+ gen_invalid(ctx);
+ break;
+ default:
+ /* invoke data storage error handler */
+ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
+ }
+ tcg_temp_free(discard);
+ tcg_temp_free(EA);
+}
+
+static void gen_stwat(DisasContext *ctx)
+{
+ gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
+}
+
+#ifdef TARGET_PPC64
+static void gen_stdat(DisasContext *ctx)
+{
+ gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
+}
#endif
static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
--
2.17.1
- [Qemu-devel] [PULL 14/35] target/ppc: Use atomic cmpxchg for STQCX, (continued)
- [Qemu-devel] [PULL 14/35] target/ppc: Use atomic cmpxchg for STQCX, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 32/35] spapr: compute default value of "hpt-max-page-size" later, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 28/35] sam460ex: Add RTC device, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 31/35] target/ppc/kvm: don't pass cpu to kvm_get_smmu_info(), David Gibson, 2018/07/03
- [Qemu-devel] [PULL 17/35] target/ppc: Split out gen_load_locked, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 16/35] target/ppc: Tidy gen_conditional_store, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 12/35] target/ppc: Use atomic load for LQ and LQARX, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 13/35] target/ppc: Use atomic store for STQ, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 25/35] hw/ppc: Give sam46ex its own config option, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 19/35] target/ppc: Split out gen_st_atomic,
David Gibson <=
- [Qemu-devel] [PULL 22/35] target/ppc: Implement the rest of gen_ld_atomic, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 23/35] target/ppc: Implement the rest of gen_st_atomic, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed store instructions, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 33/35] target/ppc: set is_jmp on ppc_tr_breakpoint_check, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, David Gibson, 2018/07/03