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[Qemu-devel] [PULL 2/8] aspeed: Implement write-1-{set, clear} for AST25
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 2/8] aspeed: Implement write-1-{set, clear} for AST2500 strapping |
Date: |
Mon, 16 Jul 2018 17:42:54 +0100 |
From: Andrew Jeffery <address@hidden>
The AST2500 SoC family changes the runtime behaviour of the hardware
strapping register (SCU70) to write-1-set/write-1-clear, with
write-1-clear implemented on the "read-only" SoC revision register
(SCU7C). For the the AST2400, the hardware strapping is
runtime-configured with read-modify-write semantics.
Signed-off-by: Andrew Jeffery <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/misc/aspeed_scu.h | 2 ++
hw/misc/aspeed_scu.c | 19 +++++++++++++++++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index f662c38188f..38996adc59f 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -41,6 +41,8 @@ typedef struct AspeedSCUState {
#define AST2500_A0_SILICON_REV 0x04000303U
#define AST2500_A1_SILICON_REV 0x04010303U
+#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
+
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define ASPEED_SCU_PROT_KEY 0x1688A8A8
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 59333b50abd..c8217740efc 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -247,11 +247,26 @@ static void aspeed_scu_write(void *opaque, hwaddr offset,
uint64_t data,
s->regs[reg] = data;
aspeed_scu_set_apb_freq(s);
break;
-
+ case HW_STRAP1:
+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+ s->regs[HW_STRAP1] |= data;
+ return;
+ }
+ /* Jump to assignment below */
+ break;
+ case SILICON_REV:
+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+ s->regs[HW_STRAP1] &= ~data;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+ /* Avoid assignment below, we've handled everything */
+ return;
case FREQ_CNTR_EVAL:
case VGA_SCRATCH1 ... VGA_SCRATCH8:
case RNG_DATA:
- case SILICON_REV:
case FREE_CNTR4:
case FREE_CNTR4_EXT:
qemu_log_mask(LOG_GUEST_ERROR,
--
2.17.1
- [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 3/8] hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq(), Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 4/8] hw/intc/arm_gic: Fix handling of GICD_ITARGETSR, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 2/8] aspeed: Implement write-1-{set, clear} for AST2500 strapping,
Peter Maydell <=
- [Qemu-devel] [PULL 1/8] target/arm: Fix LD1W and LDFF1W (scalar plus vector), Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 5/8] hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 8/8] accel/tcg: Assert that tlb fill gave us a valid TLB entry, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 6/8] bcm2835_aux: Swap RX and TX interrupt assignments, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 7/8] accel/tcg: Use correct test when looking in victim TLB for code, Peter Maydell, 2018/07/16
- Re: [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2018/07/17