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From: | Palmer Dabbelt |
Subject: | Re: [Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V |
Date: | Thu, 02 Aug 2018 10:44:32 -0700 (PDT) |
On Fri, 22 Jun 2018 12:28:14 PDT (-0700), address@hidden wrote:
Alistair Francis (5): hw/riscv/virtio: Set the soc device tree node as a simple-bus hw/riscv/virt: Increase the number of interrupts hw/riscv/virt: Connect the Xilinx PCIe hw/riscv/virt: Connect a VGA PCIe device riscv64-softmmu.mak: Build Virtio Block support default-configs/riscv32-softmmu.mak | 6 +++ default-configs/riscv64-softmmu.mak | 8 ++++ hw/riscv/virt.c | 73 ++++++++++++++++++++++++++++- include/hw/riscv/virt.h | 6 ++- 4 files changed, 90 insertions(+), 3 deletions(-)
Sorry I'm so slow here, I'm still chewing through my patch backlog. It looks like this hasn't made it upstream yet. I rebased it on top of master but have yet to figure out how to make it work, though I think that's on the Linux side.
I haven't yet looked at the code, but I like the functionality so I don't want to lose this. Can you submit a v2 that applies cleanly to master, or do you want me to deal with it?
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