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[Qemu-devel] [PATCH v7 09/80] target/mips: Check ELPA flag only in some
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v7 09/80] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 |
Date: |
Mon, 6 Aug 2018 18:59:36 +0200 |
From: Yongbok Kim <address@hidden>
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 841c0c8..bc1f21f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4896,12 +4896,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
{
const char *rn = "invalid";
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4912,6 +4911,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -4964,12 +4964,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -4981,6 +4980,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
2.7.4
- [Qemu-devel] [PATCH v7 02/80] target/mips: Avoid case statements formulated by ranges, (continued)
- [Qemu-devel] [PATCH v7 02/80] target/mips: Avoid case statements formulated by ranges, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 01/80] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 04/80] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 05/80] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 06/80] target/mips: Add CP0 BadInstrX register, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 07/80] target/mips: Add gen_op_addr_addi(), Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 08/80] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 09/80] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v7 10/80] elf: Remove duplicate preprocessor constant definition, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 11/80] elf: Add ELF flags for MIPS machine variants, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 12/80] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 13/80] linux-user: Add preprocessor availability control to some syscalls, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 14/80] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 15/80] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 16/80] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/06