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[Qemu-devel] [PATCH 6/6] softfloat: Fix missing inexact for floating-poi
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 6/6] softfloat: Fix missing inexact for floating-point add |
Date: |
Fri, 10 Aug 2018 12:31:29 -0700 |
For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15
we dropped the sticky bit and so failed to raise inexact.
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
fpu/softfloat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 8cd2400081..7d63cffdeb 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -701,7 +701,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b,
bool subtract,
}
a.frac += b.frac;
if (a.frac & DECOMPOSED_OVERFLOW_BIT) {
- a.frac >>= 1;
+ shift64RightJamming(a.frac, 1, &a.frac);
a.exp += 1;
}
return a;
--
2.17.1
- [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16, (continued)
- [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 2/6] target/arm: Ignore float_flag_input_denormal from fp_status_f16, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 3/6] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 5/6] target/arm: Fix aa64 FCADD and FCMLA decode, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 4/6] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 6/6] softfloat: Fix missing inexact for floating-point add,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH 0/6] target/arm: More sve-ish fixes, Peter Maydell, 2018/08/16