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[Qemu-devel] [PATCH v8 04/87] target/mips: Mark switch fallthroughs with
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v8 04/87] target/mips: Mark switch fallthroughs with interpretable comments |
Date: |
Mon, 13 Aug 2018 19:52:29 +0200 |
From: Aleksandar Markovic <address@hidden>
Mark switch fallthroughs with comments, in cases fallthroughs
are intentional.
The comments "/* fall through */" are interpreted by compilers and
other tools, and they will not issue warnings in such cases. For gcc,
the warning is turnend on by -Wimplicit-fallthrough. With this patch,
there will be no such warnings in target/mips directory. If such
warning appears in future, it should be checked if it is intentional,
and, if yes, marked with a comment similar to those from this patch.
The comment must be just before next "case", otherwise gcc won't
understand it.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b944ea2..3dd66b6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -14290,8 +14290,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case SDP:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- /* Fallthrough */
#endif
+ /* fall through */
case LWP:
case SWP:
gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -14301,8 +14301,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case SDM:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- /* Fallthrough */
#endif
+ /* fall through */
case LWM32:
case SWM32:
gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -20087,6 +20087,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MTHC1:
check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
+ /* fall through */
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
--
2.7.4
- [Qemu-devel] [PATCH v8 00/87] Add nanoMIPS support to QEMU, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 03/87] target/mips: Avoid case statements formulated by ranges - part 2, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 04/87] target/mips: Mark switch fallthroughs with interpretable comments,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v8 05/87] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 08/87] target/mips: Add support for availability control via bit XNP, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 01/87] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 02/87] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 09/87] target/mips: Add support for availability control via bit MT, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 11/87] target/mips: Implement CP0 Config1.WR bit functionality, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 06/87] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability control, Aleksandar Markovic, 2018/08/13