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[Qemu-devel] [PATCH v8 10/87] target/mips: Fix MT ASE instructions' avai
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability control |
Date: |
Mon, 13 Aug 2018 19:52:35 +0200 |
From: Aleksandar Rikalo <address@hidden>
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b73f434..af9714b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -8393,7 +8393,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc, int rt,
opn = "mthc0";
break;
case OPC_MFTR:
- check_insn(ctx, ASE_MT);
+ check_cp0_enabled(ctx);
if (rd == 0) {
/* Treat as NOP. */
return;
@@ -8403,7 +8403,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc, int rt,
opn = "mftr";
break;
case OPC_MTTR:
- check_insn(ctx, ASE_MT);
+ check_cp0_enabled(ctx);
gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
opn = "mttr";
@@ -18619,7 +18619,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
break;
case OPC_FORK:
- check_insn(ctx, ASE_MT);
+ check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -18632,7 +18632,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case OPC_YIELD:
- check_insn(ctx, ASE_MT);
+ check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
@@ -19929,22 +19929,22 @@ static void decode_opc(CPUMIPSState *env,
DisasContext *ctx)
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_dmt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_EMT:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_emt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_DVPE:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
--
2.7.4
- [Qemu-devel] [PATCH v8 03/87] target/mips: Avoid case statements formulated by ranges - part 2, (continued)
- [Qemu-devel] [PATCH v8 03/87] target/mips: Avoid case statements formulated by ranges - part 2, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 04/87] target/mips: Mark switch fallthroughs with interpretable comments, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 05/87] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 08/87] target/mips: Add support for availability control via bit XNP, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 01/87] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 02/87] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 09/87] target/mips: Add support for availability control via bit MT, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 11/87] target/mips: Implement CP0 Config1.WR bit functionality, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 06/87] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability control,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v8 25/87] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 12/87] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 14/87] target/mips: Add gen_op_addr_addi(), Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 16/87] elf: Add ELF flags for MIPS machine variants, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 28/87] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 33/87] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 31/87] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 22/87] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 34/87] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/13