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[Qemu-devel] [PULL 33/45] target/arm: Mask virtual interrupts if HCR_EL2
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 33/45] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set |
Date: |
Tue, 14 Aug 2018 19:18:03 +0100 |
If the "trap general exceptions" bit HCR_EL2.TGE is set, we
must mask all virtual interrupts (as per DDI0487C.a D1.14.3).
Implement this in arm_excp_unmasked().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e310ffc29d2..efb2a8d3f3d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2261,13 +2261,15 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
break;
case EXCP_VFIQ:
- if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
+ if (secure || !(env->cp15.hcr_el2 & HCR_FMO)
+ || (env->cp15.hcr_el2 & HCR_TGE)) {
/* VFIQs are only taken when hypervized and non-secure. */
return false;
}
return !(env->daif & PSTATE_F);
case EXCP_VIRQ:
- if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
+ if (secure || !(env->cp15.hcr_el2 & HCR_IMO)
+ || (env->cp15.hcr_el2 & HCR_TGE)) {
/* VIRQs are only taken when hypervized and non-secure. */
return false;
}
--
2.18.0
- [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx(), (continued)
- [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 02/45] nvic: Handle ARMv6-M SCS reserved registers, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 09/45] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 17/45] intc/arm_gic: Add virtual interface register definitions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 18/45] intc/arm_gic: Add virtualization extensions helper macros and functions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 23/45] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 25/45] intc/arm_gic: Wire the vCPU interface, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 26/45] intc/arm_gic: Implement the virtual interface registers, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 30/45] xlnx-zynqmp: Improve GIC wiring and MMIO mapping, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 29/45] intc/arm_gic: Improve traces, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 33/45] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set,
Peter Maydell <=
- [Qemu-devel] [PULL 37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 40/45] target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 43/45] target/arm: Fix typo in do_sat_addsub_64, Peter Maydell, 2018/08/14
- Re: [Qemu-devel] [PULL 00/45] target-arm queue, Peter Maydell, 2018/08/15