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Re: [Qemu-devel] [Qemu-arm] [PATCH 08/16] hw/misc/iotkit-secctl: Wire up
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [Qemu-arm] [PATCH 08/16] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs |
Date: |
Sat, 18 Aug 2018 11:05:46 +0100 |
On 18 August 2018 at 01:37, Philippe Mathieu-Daudé <address@hidden> wrote:
> On 08/09/2018 10:01 AM, Peter Maydell wrote:
>> The IoTKit does not have any Master Security Contollers itself,
>> but it does provide registers in the secure privilege control
>> block which allow control of MSCs in the external system.
>> Add support for these registers.
>>
>> Signed-off-by: Peter Maydell <address@hidden>
>> ---
>> case A_SECMSCINTEN:
>> - qemu_log_mask(LOG_UNIMP,
>> - "IoTKit SecCtl S block write: "
>> - "unimplemented offset 0x%x\n", offset);
>
> Maybe:
>
> if (value & ~0xffff) {
> GUEST_ERROR(...)
> }
We don't generally bother to log writes of raz bits as errors.
thanks
-- PMM
- [Qemu-devel] [PATCH 09/16] hw/arm/iotkit: Wire up the lines for MSCs, (continued)
- [Qemu-devel] [PATCH 09/16] hw/arm/iotkit: Wire up the lines for MSCs, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 11/16] hw/dma/pl080: Support all three interrupt lines, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 01/16] hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 12/16] hw/dma/pl080: Don't use CPU address space for DMA accesses, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 08/16] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 14/16] hw/dma/pl080: Correct bug in register address decode logic, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 16/16] hw/arm/mps2-tz: Create PL081s and MSCs, Peter Maydell, 2018/08/09
- Re: [Qemu-devel] [Qemu-arm] [PATCH 00/16] arm: Implement MPS2 watchdogs and DMA, Peter Maydell, 2018/08/16