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[Qemu-devel] [PULL v4 28/46] target/mips: Implement MT ASE support for n
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v4 28/46] target/mips: Implement MT ASE support for nanoMIPS |
Date: |
Thu, 23 Aug 2018 15:34:18 +0200 |
From: Stefan Markovic <address@hidden>
Add emulation of MT ASE instructions for nanoMIPS.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e0eb7e4..95632dd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16989,7 +16989,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
-static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
+static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
int rt = extract32(ctx->opcode, 21, 5);
int rs = extract32(ctx->opcode, 16, 5);
@@ -17157,6 +17157,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext
*ctx)
tcg_temp_free(t0);
}
break;
+ case NM_D_E_MT_VPE:
+ {
+ uint8_t sc = extract32(ctx->opcode, 10, 1);
+ TCGv t0 = tcg_temp_new();
+
+ switch (sc) {
+ case 0:
+ if (rs == 1) {
+ /* DMT */
+ check_cp0_mt(ctx);
+ gen_helper_dmt(t0);
+ gen_store_gpr(t0, rt);
+ } else if (rs == 0) {
+ /* DVPE */
+ check_cp0_mt(ctx);
+ gen_helper_dvpe(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ case 1:
+ if (rs == 1) {
+ /* EMT */
+ check_cp0_mt(ctx);
+ gen_helper_emt(t0);
+ gen_store_gpr(t0, rt);
+ } else if (rs == 0) {
+ /* EVPE */
+ check_cp0_mt(ctx);
+ gen_helper_evpe(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ }
+
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_FORK:
+ check_mt(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+ gen_helper_fork(t0, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ case NM_MFTR:
+ case NM_MFHTR:
+ check_cp0_enabled(ctx);
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return;
+ }
+ gen_mftr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
+ extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
+ break;
+ case NM_MTTR:
+ case NM_MTHTR:
+ check_cp0_enabled(ctx);
+ gen_mttr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
+ extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
+ break;
+ case NM_YIELD:
+ check_mt(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_helper_yield(t0, cpu_env, t0);
+ gen_store_gpr(t0, rt);
+ tcg_temp_free(t0);
+ }
+ break;
#endif
default:
generate_exception_end(ctx, EXCP_RI);
@@ -18049,7 +18130,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
case NM_POOL32A:
switch (ctx->opcode & 0x07) {
case NM_POOL32A0:
- gen_pool32a0_nanomips_insn(ctx);
+ gen_pool32a0_nanomips_insn(env, ctx);
break;
case NM_POOL32A7:
switch (extract32(ctx->opcode, 3, 3)) {
--
2.7.4
- [Qemu-devel] [PULL v4 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, (continued)
- [Qemu-devel] [PULL v4 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 37/46] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 31/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 28/46] target/mips: Implement MT ASE support for nanoMIPS,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v4 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 17/46] target/mips: Add emulation of nanoMIPS FP instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 23/46] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 32/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 44/46] mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 39/46] elf: Add EM_NANOMIPS value as a valid one for e_machine field, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 36/46] disas: Add support for nanoMIPS platform, Aleksandar Markovic, 2018/08/23