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[Qemu-devel] [PULL v5 01/46] target/mips: Add preprocessor constants for
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v5 01/46] target/mips: Add preprocessor constants for nanoMIPS |
Date: |
Thu, 23 Aug 2018 16:18:16 +0200 |
From: Aleksandar Markovic <address@hidden>
Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/mips-defs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index d239069..c8e9979 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -39,6 +39,7 @@
#define ISA_MIPS64R5 0x00001000
#define ISA_MIPS32R6 0x00002000
#define ISA_MIPS64R6 0x00004000
+#define ISA_NANOMIPS32 0x00008000
/* MIPS ASEs. */
#define ASE_MIPS16 0x00010000
@@ -87,6 +88,9 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
+/* Wave Computing: "nanoMIPS" */
+#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
--
2.7.4
- [Qemu-devel] [PULL v5 00/46] MIPS queue August 2018 v5, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 01/46] target/mips: Add preprocessor constants for nanoMIPS,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v5 13/46] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 03/46] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 06/46] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 08/46] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 12/46] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Aleksandar Markovic, 2018/08/23