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[Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up |
Date: |
Fri, 24 Aug 2018 10:33:01 +0100 |
For the A15MPCore internal peripheral object, we handle GIC
security extensions support by checking whether the CPUs
have EL3 enabled; if so then we enable it also on the GIC.
Handle the virtualization extensions in the same way: if the
CPU has EL2 then enable it on the GIC and wire up the
virtualization-specific memory regions and the maintenance
interrupt.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
hw/cpu/a15mpcore.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 43c10794938..226ce8900f2 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -53,6 +53,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
int i;
Error *err = NULL;
bool has_el3;
+ bool has_el2;
Object *cpuobj;
gicdev = DEVICE(&s->gic);
@@ -67,6 +68,10 @@ static void a15mp_priv_realize(DeviceState *dev, Error
**errp)
has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
+ /* Similarly for virtualization support */
+ has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
+ object_property_get_bool(cpuobj, "has_el2", &error_abort);
+ qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
}
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
@@ -103,20 +108,40 @@ static void a15mp_priv_realize(DeviceState *dev, Error
**errp)
qdev_get_gpio_in(gicdev,
ppibase + timer_irq[irq]));
}
+ if (has_el2) {
+ /* Connect the GIC maintenance interrupt to PPI ID 25 */
+ sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
+ qdev_get_gpio_in(gicdev, ppibase + 25));
+ }
}
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x0000-0x0fff -- reserved
* 0x1000-0x1fff -- GIC Distributor
* 0x2000-0x3fff -- GIC CPU interface
- * 0x4000-0x4fff -- GIC virtual interface control (not modelled)
- * 0x5000-0x5fff -- GIC virtual interface control (not modelled)
- * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
+ * 0x4000-0x4fff -- GIC virtual interface control for this CPU
+ * 0x5000-0x51ff -- GIC virtual interface control for CPU 0
+ * 0x5200-0x53ff -- GIC virtual interface control for CPU 1
+ * 0x5400-0x55ff -- GIC virtual interface control for CPU 2
+ * 0x5600-0x57ff -- GIC virtual interface control for CPU 3
+ * 0x6000-0x7fff -- GIC virtual CPU interface
*/
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(&s->container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
+ if (has_el2) {
+ memory_region_add_subregion(&s->container, 0x4000,
+ sysbus_mmio_get_region(busdev, 2));
+ memory_region_add_subregion(&s->container, 0x6000,
+ sysbus_mmio_get_region(busdev, 3));
+ for (i = 0; i < s->num_cpu; i++) {
+ hwaddr base = 0x5000 + i * 0x200;
+ MemoryRegion *mr = sysbus_mmio_get_region(busdev,
+ 4 + s->num_cpu + i);
+ memory_region_add_subregion(&s->container, base, mr);
+ }
+ }
}
static Property a15mp_priv_properties[] = {
--
2.18.0
- [Qemu-devel] [PULL 06/52] hw/arm/vexpress: Connect VIRQ and VFIQ, (continued)
- [Qemu-devel] [PULL 06/52] hw/arm/vexpress: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 05/52] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 01/52] softfloat: Add scaling int-to-float routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 08/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up,
Peter Maydell <=
- [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 19/52] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 14/52] target/arm: Implement AArch32 HCR and HCR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 20/52] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 21/52] hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 22/52] hw/arm/iotkit: Wire up the dualtimer, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 23/52] hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 24/52] hw/arm/iotkit: Wire up the watchdogs, Peter Maydell, 2018/08/24