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[Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry |
Date: |
Fri, 24 Aug 2018 10:33:08 +0100 |
On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).
Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 10f40b01700..b0ab18af43e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8054,6 +8054,8 @@ static void take_aarch32_exception(CPUARMState *env, int
new_mode,
if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
env->uncached_cpsr |= CPSR_E;
}
+ /* J and IL must always be cleared for exception entry */
+ env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
env->daif |= mask;
if (new_mode == ARM_CPU_MODE_HYP) {
--
2.18.0
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, (continued)
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 19/52] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 14/52] target/arm: Implement AArch32 HCR and HCR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry,
Peter Maydell <=
- [Qemu-devel] [PULL 20/52] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 21/52] hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 22/52] hw/arm/iotkit: Wire up the dualtimer, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 23/52] hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 24/52] hw/arm/iotkit: Wire up the watchdogs, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 25/52] hw/arm/iotkit: Wire up the S32KTIMER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 26/52] hw/misc/iotkit-sysctl: Implement IoTKit system control element, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 28/52] hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 27/52] hw/misc/iotkit-sysinfo: Implement IoTKit system information block, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 31/52] hw/arm/iotkit: Wire up the lines for MSCs, Peter Maydell, 2018/08/24