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Re: [Qemu-devel] [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M
From: |
Janeczek, Craig |
Subject: |
Re: [Qemu-devel] [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I |
Date: |
Tue, 28 Aug 2018 17:29:33 +0000 |
The only commands that have the 5th bit required to address XR16 are
S32M2I/S32I2M.
I can split it out into a separate utility function and put a conditional into
the S32M2I/S32I2M functions if you are more comfortable with that.
-----Original Message-----
From: Aleksandar Markovic <address@hidden>
Sent: Tuesday, August 28, 2018 12:53 PM
To: Janeczek, Craig <address@hidden>; address@hidden
Cc: address@hidden
Subject: Re: [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I
> > This does not handle the case xra == XR16.
> I do not see where the case is un-handled. XR16 maps to index 15 in the
> mxu_gpr array.
But, XR16 has its own rules for read/write, and you are treating it just as a
regular register.
[Qemu-devel] [PATCH v3 6/8] target/mips: Add MXU instruction D16MAC, Craig Janeczek, 2018/08/28
[Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Craig Janeczek, 2018/08/28
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Aleksandar Markovic, 2018/08/28
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Janeczek, Craig, 2018/08/28
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Aleksandar Markovic, 2018/08/28
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Janeczek, Craig, 2018/08/28
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Aleksandar Markovic, 2018/08/28
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, Janeczek, Craig, 2018/08/28