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[Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and
From: |
Craig Janeczek |
Subject: |
[Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR |
Date: |
Thu, 30 Aug 2018 15:30:19 -0400 |
Adds support for emulating the S32LDD and S32LDDR MXU instructions.
Signed-off-by: Craig Janeczek <address@hidden>
---
v1
- initial patch
v2
- changed bitfield usage to extract32
v3
- Split gen_mxu function into command specific gen_mxu_<ins> functions
v4
- Add check for MXUEN
target/mips/translate.c | 49 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 31c7342261..297f913d36 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4222,6 +4222,51 @@ static void gen_mxu_q8mul(DisasContext *ctx, uint32_t
opc)
tcg_temp_free(t7);
}
+/* S32LDD XRa, rb, S12 - Load a word from memory to XRF
+ * S32LDDR XRa, rb, S12 - Load a word from memory to XRF,
+ * reversed byte sequence */
+static void gen_mxu_s32ldd(DisasContext *ctx, uint32_t opc)
+{
+ TCGv t0, t1;
+ TCGLabel *l0;
+ uint32_t xra, s12, sel, rb;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ l0 = gen_new_label();
+
+ xra = extract32(ctx->opcode, 6, 4);
+ s12 = extract32(ctx->opcode, 10, 10);
+ sel = extract32(ctx->opcode, 20, 1);
+ rb = extract32(ctx->opcode, 21, 5);
+
+ gen_load_mxu_cr(t0);
+ tcg_gen_andi_tl(t0, t0, MXUEN);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0);
+
+ gen_load_gpr(t0, rb);
+
+ tcg_gen_movi_tl(t1, s12);
+ tcg_gen_shli_tl(t1, t1, 2);
+ if (s12 & 0x200) {
+ tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
+ }
+ tcg_gen_add_tl(t1, t0, t1);
+ tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL);
+
+ if (sel == 1) {
+ /* S32LDDR */
+ tcg_gen_bswap32_tl(t1, t1);
+ }
+ gen_store_mxu_gpr(t1, xra);
+
+ gen_set_label(l0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
/* Godson integer instructions */
static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
@@ -18310,6 +18355,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *env,
DisasContext *ctx)
gen_mxu_q8mul(ctx, op1);
break;
+ case OPC_MXU_S32LDD:
+ gen_mxu_s32ldd(ctx, op1);
+ break;
+
default: /* Invalid */
MIPS_INVAL("special2_mxu");
generate_exception_end(ctx, EXCP_RI);
--
2.18.0
- [Qemu-devel] [PATCH v4 0/9] Add limited MXU instruction support, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction handling, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 4/9] target/mips: Add MXU instructions S32I2M and S32M2I, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR,
Craig Janeczek <=
- [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 8/9] target/mips: Add MXU instructions Q8MUL and Q8MULSU, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 6/9] target/mips: Add MXU instruction D16MUL, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 7/9] target/mips: Add MXU instruction D16MAC, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD, Craig Janeczek, 2018/08/30