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Re: [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI e
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only |
Date: |
Mon, 17 Sep 2018 01:45:08 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 9/16/18 5:04 PM, Fredrik Noring wrote:
> The Linux kernel traps and emulates certain instructions. For user only,
> QEMU is the kernel, so we emulate those traps by simply emulating the
> instructions directly.
>
> Signed-off-by: Fredrik Noring <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/mips/translate.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c35be0053b..77d678353e 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1887,6 +1887,20 @@ static inline void check_insn_opc_removed(DisasContext
> *ctx, int flags)
> }
> }
>
> +/*
> + * Unless user only, when the kernel emulates the code, a "reserved
> + * instruction" exception is generated if the CPU has corresponding
> + * flag set which indicates that the instruction has been removed.
> + */
> +static inline void check_insn_opc_user_only(DisasContext *ctx, int flags)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (unlikely(ctx->insn_flags & flags)) {
> + generate_exception_end(ctx, EXCP_RI);
> + }
> +#endif
> +}
> +
> /* This code generates a "reserved instruction" exception if the
> CPU does not support 64-bit paired-single (PS) floating point data type */
> static inline void check_ps(DisasContext *ctx)
>
- [Qemu-devel] [PATCH v4 6/8] target/mips: Define the R5900 CPU, (continued)
- Re: [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Maciej W. Rozycki, 2018/09/17
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/18
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Maciej W. Rozycki, 2018/09/18
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/19
- Re: [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only,
Philippe Mathieu-Daudé <=
- Re: [Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Philippe Mathieu-Daudé, 2018/09/16
Re: [Qemu-devel] [PATCH v4 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Philippe Mathieu-Daudé, 2018/09/16