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[Qemu-devel] [PATCH v6 7/7] elf: Toshiba/Sony rather than MIPS are the i
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v6 7/7] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900 |
Date: |
Sat, 15 Sep 2018 12:28:05 +0200 |
Sources [1][2] indicate that the Emotion Engine was designed by Toshiba
and licensed to Sony. Others [3][4][5] claim it was a joint effort. It
therefore makes sense to refer to the CPU as "Toshiba/Sony R5900".
[1]
http://cs.nyu.edu/courses/spring02/V22.0480-002/projects/aldrich/emotionengine.ppt
[2] http://archive.arstechnica.com/reviews/1q00/playstation2/m-ee-3.html
[3]
http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/emotionengine%20(mpr).pdf
[4] http://www.eetimes.com/document.asp?doc_id=1144055
[5] https://www.toshiba.co.jp/about/press/2001_09/pr2701.htm
Reported-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
---
include/elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index 312f68af81..2510fc7be4 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -76,7 +76,7 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */
#define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */
#define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */
-#define EF_MIPS_MACH_5900 0x00920000 /* MIPS R5900 */
+#define EF_MIPS_MACH_5900 0x00920000 /* Toshiba/Sony R5900 */
#define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */
#define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra's RM9000 */
#define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */
--
2.16.4
- [Qemu-devel] [PATCH v6 0/7] target/mips: Limited support for the R5900, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 1/7] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 5/7] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 4/7] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 7/7] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900,
Fredrik Noring <=
- [Qemu-devel] [PATCH v6 6/7] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/29