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Re: [Qemu-devel] [PATCH v1 3/3] intel-iommu: search iotlb for levels sup
From: |
Peter Xu |
Subject: |
Re: [Qemu-devel] [PATCH v1 3/3] intel-iommu: search iotlb for levels supported by the address width. |
Date: |
Mon, 12 Nov 2018 17:36:38 +0800 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Nov 12, 2018 at 05:25:48PM +0800, Yu Zhang wrote:
> On Mon, Nov 12, 2018 at 04:51:22PM +0800, Peter Xu wrote:
> > On Fri, Nov 09, 2018 at 07:49:47PM +0800, Yu Zhang wrote:
> > > This patch updates vtd_lookup_iotlb() to search cached mappings only
> > > for all page levels supported by address width of current vIOMMU. Also,
> > > to cover 57-bit width, the shift of source id(VTD_IOTLB_SID_SHIFT) and
> > > of page level(VTD_IOTLB_LVL_SHIFT) are enlarged by 9 - the stride of
> > > one paging structure level.
> > >
> > > Signed-off-by: Yu Zhang <address@hidden>
> > > ---
> > > Cc: "Michael S. Tsirkin" <address@hidden>
> > > Cc: Marcel Apfelbaum <address@hidden>
> > > Cc: Paolo Bonzini <address@hidden>
> > > Cc: Richard Henderson <address@hidden>
> > > Cc: Eduardo Habkost <address@hidden>
> > > Cc: Peter Xu <address@hidden>
> > > ---
> > > hw/i386/intel_iommu.c | 5 +++--
> > > hw/i386/intel_iommu_internal.h | 7 ++-----
> > > 2 files changed, 5 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > index 9cdf755..ce7e17e 100644
> > > --- a/hw/i386/intel_iommu.c
> > > +++ b/hw/i386/intel_iommu.c
> > > @@ -254,11 +254,12 @@ static uint64_t vtd_get_iotlb_gfn(hwaddr addr,
> > > uint32_t level)
> > > static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t
> > > source_id,
> > > hwaddr addr)
> > > {
> > > - VTDIOTLBEntry *entry;
> > > + VTDIOTLBEntry *entry = NULL;
> > > uint64_t key;
> > > int level;
> > > + int max_level = (s->aw_bits - VTD_PAGE_SHIFT_4K) / VTD_SL_LEVEL_BITS;
> > >
> > > - for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
> > > + for (level = VTD_SL_PT_LEVEL; level < max_level; level++) {
> >
> > My understanding of current IOTLB is that it only caches the last
> > level of mapping, say:
> >
> > - level 1: 4K page
> > - level 2: 2M page
> > - level 3: 1G page
> >
> > So we don't check against level=4 even if x-aw-bits=48 is specified.
> >
> > Here does it mean that we're going to have... 512G iommu huge pages?
> >
>
> No. My bad, I misunderstood this routine. And now I believe we do not
> need this patch. :-)
Yeah good to confirm that :-)
Regards,
--
Peter Xu
- [Qemu-devel] [PATCH v1 2/3] intel-iommu: extend VTD emulation to allow 57-bit IOVA address width., (continued)
[Qemu-devel] [PATCH v1 3/3] intel-iommu: search iotlb for levels supported by the address width., Yu Zhang, 2018/11/09
Re: [Qemu-devel] [PATCH v1 0/3] intel-iommu: add support for 5-level virtual IOMMU., no-reply, 2018/11/09
Re: [Qemu-devel] [PATCH v1 0/3] intel-iommu: add support for 5-level virtual IOMMU., Peter Xu, 2018/11/12