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[Qemu-devel] [PULL 03/11] target/mips: Fix decoding mechanism of R5900 D
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 03/11] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 |
Date: |
Sat, 17 Nov 2018 16:54:32 +0100 |
From: Fredrik Noring <address@hidden>
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
target/mips/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8601333..3ddd700 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4743,6 +4743,63 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,
int rd, int rs, int rt)
tcg_temp_free(t1);
}
+static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ switch (opc) {
+ case TX79_MMI_DIV1:
+ {
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ext32s_tl(t1, t1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
+ tcg_gen_and_tl(t2, t2, t3);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
+ tcg_gen_or_tl(t2, t2, t3);
+ tcg_gen_movi_tl(t3, 0);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_div_tl(cpu_LO[1], t0, t1);
+ tcg_gen_rem_tl(cpu_HI[1], t0, t1);
+ tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
+ tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
+ tcg_temp_free(t3);
+ tcg_temp_free(t2);
+ }
+ break;
+ case TX79_MMI_DIVU1:
+ {
+ TCGv t2 = tcg_const_tl(0);
+ TCGv t3 = tcg_const_tl(1);
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
+ tcg_gen_divu_tl(cpu_LO[1], t0, t1);
+ tcg_gen_remu_tl(cpu_HI[1], t0, t1);
+ tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
+ tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
+ tcg_temp_free(t3);
+ tcg_temp_free(t2);
+ }
+ break;
+ default:
+ MIPS_INVAL("div1 TX79");
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ }
+ out:
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
static void gen_muldiv(DisasContext *ctx, uint32_t opc,
int acc, int rs, int rt)
{
@@ -4755,14 +4812,11 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
if (acc != 0) {
- if (!(ctx->insn_flags & INSN_R5900)) {
- check_dsp(ctx);
- }
+ check_dsp(ctx);
}
switch (opc) {
case OPC_DIV:
- case TX79_MMI_DIV1:
{
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
@@ -4784,7 +4838,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
break;
case OPC_DIVU:
- case TX79_MMI_DIVU1:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
@@ -26525,7 +26578,7 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
break;
case TX79_MMI_DIV1:
case TX79_MMI_DIVU1:
- gen_muldiv(ctx, opc, 1, rs, rt);
+ gen_div1_tx79(ctx, opc, rs, rt);
break;
case TX79_MMI_MTLO1:
case TX79_MMI_MTHI1:
--
2.7.4
- [Qemu-devel] [PULL 00/11] MIPS queue for November 2018 (for QEMU 3.1-rc2), Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 01/11] linux-user: Update MIPS specific prctl() implementation, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 02/11] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 11/11] MAINTAINERS: Add Stefan Markovic as a MIPS reviewer, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 03/11] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 10/11] target/mips: Disable R5900 support, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 09/11] target/mips: Rename MMI-related functions, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 07/11] target/mips: Rename MMI-related masks, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 05/11] target/mips: Guard check_insn_opc_user_only with INSN_R5900 check, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 04/11] target/mips: Fix decoding mechanism of special R5900 opcodes, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 06/11] target/mips: Guard check_insn with INSN_R5900 check, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 08/11] target/mips: Rename MMI-related opcodes, Aleksandar Markovic, 2018/11/17
- Re: [Qemu-devel] [PULL 00/11] MIPS queue for November 2018 (for QEMU 3.1-rc2), Philippe Mathieu-Daudé, 2018/11/17