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[Qemu-devel] [PULL 05/11] target/mips: Guard check_insn_opc_user_only wi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 05/11] target/mips: Guard check_insn_opc_user_only with INSN_R5900 check |
Date: |
Sat, 17 Nov 2018 16:54:34 +0100 |
From: Fredrik Noring <address@hidden>
Avoid using check_opc_user_only() as a decision making code wrt
various architectures. Use ctx->insn_flags checks instead.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a21b277..c79da3c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28313,7 +28313,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_LL: /* Load and stores */
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_user_only(ctx, INSN_R5900);
+ if (ctx->insn_flags & INSN_R5900) {
+ check_insn_opc_user_only(ctx, INSN_R5900);
+ }
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
@@ -28339,7 +28341,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
- check_insn_opc_user_only(ctx, INSN_R5900);
+ if (ctx->insn_flags & INSN_R5900) {
+ check_insn_opc_user_only(ctx, INSN_R5900);
+ }
gen_st_cond(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
@@ -28607,7 +28611,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LLD:
- check_insn_opc_user_only(ctx, INSN_R5900);
+ if (ctx->insn_flags & INSN_R5900) {
+ check_insn_opc_user_only(ctx, INSN_R5900);
+ }
/* fall through */
case OPC_LDL:
case OPC_LDR:
@@ -28631,7 +28637,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
case OPC_SCD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS3);
- check_insn_opc_user_only(ctx, INSN_R5900);
+ if (ctx->insn_flags & INSN_R5900) {
+ check_insn_opc_user_only(ctx, INSN_R5900);
+ }
check_mips_64(ctx);
gen_st_cond(ctx, op, rt, rs, imm);
break;
--
2.7.4
- [Qemu-devel] [PULL 00/11] MIPS queue for November 2018 (for QEMU 3.1-rc2), Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 01/11] linux-user: Update MIPS specific prctl() implementation, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 02/11] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 11/11] MAINTAINERS: Add Stefan Markovic as a MIPS reviewer, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 03/11] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 10/11] target/mips: Disable R5900 support, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 09/11] target/mips: Rename MMI-related functions, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 07/11] target/mips: Rename MMI-related masks, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 05/11] target/mips: Guard check_insn_opc_user_only with INSN_R5900 check,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 04/11] target/mips: Fix decoding mechanism of special R5900 opcodes, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 06/11] target/mips: Guard check_insn with INSN_R5900 check, Aleksandar Markovic, 2018/11/17
- [Qemu-devel] [PULL 08/11] target/mips: Rename MMI-related opcodes, Aleksandar Markovic, 2018/11/17
- Re: [Qemu-devel] [PULL 00/11] MIPS queue for November 2018 (for QEMU 3.1-rc2), Philippe Mathieu-Daudé, 2018/11/17