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Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext |
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Date: |
Tue, 15 Jan 2019 14:25:44 -0800 |
On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
<address@hidden> wrote:
>
> On 1/15/19 10:58 AM, Alistair Francis wrote:
> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> > *cs)
> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> > *cpu)
>
> Why change this? I know there is variation in the naming, but my
> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
Good point, I have changed it back to cs.
Alistair
>
> Otherwise,
> Reviewed-by: Richard Henderson <address@hidden>
>
>
> r~
- [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3, Alistair Francis, 2019/01/14
- [Qemu-devel] [PATCH v1 1/8] RISC-V: Split out mstatus_fs from tb_flags, Alistair Francis, 2019/01/14
- [Qemu-devel] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty, Alistair Francis, 2019/01/14
- [Qemu-devel] [PATCH v1 3/8] RISC-V: Implement mstatus.TSR/TW/TVM, Alistair Francis, 2019/01/14
- [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext, Alistair Francis, 2019/01/14
- [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers, Alistair Francis, 2019/01/14
- [Qemu-devel] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate, Alistair Francis, 2019/01/14