[Qemu-devel] [PATCH 4/8] target/ppc: Optimize emulation of vgbbd instruction

[Stefan Brankovic]

Optimize altivec instruction vgbbd (Vector Gather Bits by Bytes by Doubleword)
All ith bits (i in range 1 to 8) of each byte of doubleword element in
source register are concatenated and placed into ith byte of appropriate
doubleword element in destination register.

Following solution is done for every doubleword element of source register
(placed in shifted variable):
We gather bits in 2x8 iterations.
In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of byte 8 are
in their final spots so we just and avr with mask. For every next iteration,
we have to shift right both shifted(7 places) and mask(8 places), so we get
bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in right places so we and
shifted with new value of mask... After first 8 iteration(first for loop) we
have all first bits in their final place all second bits but second bit from
eight byte in their place,... only 1 eight bit from eight byte is in it's
place), so we and result1 with mask1 to save those bits that are at right
place and save them in result1. In second loop we do all operations
symetrical, so we get other half of bits on their final spots, and save
result in result2. Or of result1 and result2 is placed in appropriate
doubleword element of vD. We repeat this 2 times.

Signed-off-by: Stefan Brankovic <address@hidden>
---
 target/ppc/translate/vmx-impl.inc.c | 99 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 98 insertions(+), 1 deletion(-)

diff --git a/target/ppc/translate/vmx-impl.inc.c 
b/target/ppc/translate/vmx-impl.inc.c
index 87f69dc..010f337 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -780,6 +780,103 @@ static void trans_vsr(DisasContext *ctx)
     tcg_temp_free_i64(tmp);
 }
 
+/*
+ * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
+ *
+ * All ith bits (i in range 1 to 8) of each byte of doubleword element in 
source
+ * register are concatenated and placed into ith byte of appropriate doubleword
+ * element in destination register.
+ *
+ * Following solution is done for every doubleword element of source register
+ * (placed in shifted variable):
+ * We gather bits in 2x8 iterations.
+ * In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of byte 8 are
+ * in their final spots so we just and avr with mask. For every next iteration,
+ * we have to shift right both shifted(7 places) and mask(8 places), so we get
+ * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in right places so we and
+ * shifted with new value of mask... After first 8 iteration(first for loop) we
+ * have all first bits in their final place all second bits but second bit from
+ * eight byte in their place,... only 1 eight bit from eight byte is in it's
+ * place), so we and result1 with mask1 to save those bits that are at right
+ * place and save them in result1. In second loop we do all operations
+ * symetrical, so we get other half of bits on their final spots, and save
+ * result in result2. Or of result1 and result2 is placed in appropriate
+ * doubleword element of vD. We repeat this 2 times.
+ */
+static void trans_vgbbd(DisasContext *ctx)
+{
+    int VT = rD(ctx->opcode);
+    int VB = rB(ctx->opcode);
+    TCGv_i64 tmp = tcg_temp_new_i64();
+    TCGv_i64 avr = tcg_temp_new_i64();
+    TCGv_i64 shifted = tcg_temp_new_i64();
+    TCGv_i64 result1 = tcg_temp_new_i64();
+    TCGv_i64 result2 = tcg_temp_new_i64();
+    uint64_t mask = 0x8040201008040201ULL;
+    uint64_t mask1 = 0x80c0e0f0f8fcfeffULL;
+    uint64_t mask2 = 0x7f3f1f0f07030100ULL;
+    int i;
+
+    get_avr64(avr, VB, true);
+    tcg_gen_movi_i64(result1, 0x0ULL);
+    tcg_gen_mov_i64(shifted, avr);
+    for (i = 0; i < 8; i++) {
+        tcg_gen_andi_i64(tmp, shifted, mask);
+        tcg_gen_or_i64(result1, result1, tmp);
+
+        tcg_gen_shri_i64(shifted, shifted, 7);
+        mask = mask >> 8;
+    }
+    tcg_gen_andi_i64(result1, result1, mask1);
+
+    mask = 0x8040201008040201ULL;
+    tcg_gen_movi_i64(result2, 0x0ULL);
+    for (i = 0; i < 8; i++) {
+        tcg_gen_andi_i64(tmp, avr, mask);
+        tcg_gen_or_i64(result2, result2, tmp);
+
+        tcg_gen_shli_i64(avr, avr, 7);
+        mask = mask << 8;
+    }
+    tcg_gen_andi_i64(result2, result2, mask2);
+
+    tcg_gen_or_i64(result2, result2, result1);
+    set_avr64(VT, result2, true);
+
+    mask = 0x8040201008040201ULL;
+    get_avr64(avr, VB, false);
+    tcg_gen_movi_i64(result1, 0x0ULL);
+    tcg_gen_mov_i64(shifted, avr);
+    for (i = 0; i < 8; i++) {
+        tcg_gen_andi_i64(tmp, shifted, mask);
+        tcg_gen_or_i64(result1, result1, tmp);
+
+        tcg_gen_shri_i64(shifted, shifted, 7);
+        mask = mask >> 8;
+    }
+    tcg_gen_andi_i64(result1, result1, mask1);
+
+    mask = 0x8040201008040201ULL;
+    tcg_gen_movi_i64(result2, 0x0ULL);
+    for (i = 0; i < 8; i++) {
+        tcg_gen_andi_i64(tmp, avr, mask);
+        tcg_gen_or_i64(result2, result2, tmp);
+
+        tcg_gen_shli_i64(avr, avr, 7);
+        mask = mask << 8;
+    }
+    tcg_gen_andi_i64(result2, result2, mask2);
+
+    tcg_gen_or_i64(result2, result2, result1);
+    set_avr64(VT, result2, false);
+
+    tcg_temp_free_i64(tmp);
+    tcg_temp_free_i64(avr);
+    tcg_temp_free_i64(shifted);
+    tcg_temp_free_i64(result1);
+    tcg_temp_free_i64(result2);
+}
+
 GEN_VXFORM(vmuloub, 4, 0);
 GEN_VXFORM(vmulouh, 4, 1);
 GEN_VXFORM(vmulouw, 4, 2);
@@ -1319,7 +1416,7 @@ GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
                 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
 GEN_VXFORM(vbpermd, 6, 23);
 GEN_VXFORM(vbpermq, 6, 21);
-GEN_VXFORM_NOA(vgbbd, 6, 20);
+GEN_VXFORM_TRANS(vgbbd, 6, 20);
 GEN_VXFORM(vpmsumb, 4, 16)
 GEN_VXFORM(vpmsumh, 4, 17)
 GEN_VXFORM(vpmsumw, 4, 18)
-- 
2.7.4