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[Qemu-devel] [PATCH v18 14/29] target/rx: Convert to CPUClass::tlb_fill
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v18 14/29] target/rx: Convert to CPUClass::tlb_fill |
Date: |
Fri, 7 Jun 2019 17:37:10 +0200 |
From: Richard Henderson <address@hidden>
The interface for tlb_fill has changed very recently.
Move the function into cpu.c so that it may be static
while assigning to the CPUClass methods.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yoshinori Sato <address@hidden>
Message-Id: <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/rx/cpu.c | 14 ++++++++++++++
target/rx/op_helper.c | 11 -----------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index c370f65faa..3eef1329a1 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -154,6 +154,19 @@ static void rx_cpu_disas_set_info(CPUState *cpu,
disassemble_info *info)
info->print_insn = print_insn_rx;
}
+static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
+{
+ uint32_t address, physical, prot;
+
+ /* Linear mapping */
+ address = physical = addr & TARGET_PAGE_MASK;
+ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+ return true;
+}
+
static void rx_cpu_init(Object *obj)
{
CPUState *cs = CPU(obj);
@@ -188,6 +201,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void
*data)
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->tcg_initialize = rx_translate_init;
+ cc->tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
}
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 9a460070e9..fb7ae3c3ec 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -468,14 +468,3 @@ void QEMU_NORETURN helper_rxbrk(CPURXState *env)
{
raise_exception(env, 0x100, 0);
}
-
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
- uint32_t address, physical, prot;
-
- /* Linear mapping */
- address = physical = addr & TARGET_PAGE_MASK;
- prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
-}
--
2.20.1
- [Qemu-devel] [PATCH v18 04/29] !fixup target/rx: CPU definition, (continued)
- [Qemu-devel] [PATCH v18 15/29] target/rx: Add RX to SysEmuTarget, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 19/29] MAINTAINERS: Add RX, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 17/29] hw/rx: Honor -accel qtest, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 16/29] tests: Add rx to machine-none-test.c, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 14/29] target/rx: Convert to CPUClass::tlb_fill,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v18 12/29] qemu/bitops.h: Add extract8 and extract16, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 13/29] hw/registerfields.h: Add 8bit and 16bit register macros, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 05/29] !fixup target/rx: CPU definition, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 09/29] hw/char: RX62N serial communication interface (SCI), Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 07/29] hw/intc: RX62N interrupt controller (ICUa), Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 02/29] target/rx: TCG helper, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 03/29] target/rx: CPU definition, Philippe Mathieu-Daudé, 2019/06/07
- [Qemu-devel] [PATCH v18 08/29] hw/timer: RX62N internal timer modules, Philippe Mathieu-Daudé, 2019/06/07