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[Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decod
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decodetree |
Date: |
Thu, 13 Jun 2019 13:14:06 +0100 |
Convert the VFP single load/store insns VLDR and VSTR to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 73 ++++++++++++++++++++++++++++++++++
target/arm/translate.c | 22 +---------
target/arm/vfp.decode | 7 ++++
3 files changed, 82 insertions(+), 20 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 5f081221b83..40f2cac3e2e 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -853,3 +853,76 @@ static bool trans_VMOV_64_dp(DisasContext *s,
arg_VMOV_64_sp *a)
return true;
}
+
+static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
+{
+ uint32_t offset;
+ TCGv_i32 addr;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ offset = a->imm << 2;
+ if (!a->u) {
+ offset = -offset;
+ }
+
+ if (s->thumb && a->rn == 15) {
+ /* This is actually UNPREDICTABLE */
+ addr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(addr, s->pc & ~2);
+ } else {
+ addr = load_reg(s, a->rn);
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+ if (a->l) {
+ gen_vfp_ld(s, false, addr);
+ gen_mov_vreg_F0(false, a->vd);
+ } else {
+ gen_mov_F0_vreg(false, a->vd);
+ gen_vfp_st(s, false, addr);
+ }
+ tcg_temp_free_i32(addr);
+
+ return true;
+}
+
+static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a)
+{
+ uint32_t offset;
+ TCGv_i32 addr;
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ offset = a->imm << 2;
+ if (!a->u) {
+ offset = -offset;
+ }
+
+ if (s->thumb && a->rn == 15) {
+ /* This is actually UNPREDICTABLE */
+ addr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(addr, s->pc & ~2);
+ } else {
+ addr = load_reg(s, a->rn);
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+ if (a->l) {
+ gen_vfp_ld(s, true, addr);
+ gen_mov_vreg_F0(true, a->vd);
+ } else {
+ gen_mov_F0_vreg(true, a->vd);
+ gen_vfp_st(s, true, addr);
+ }
+ tcg_temp_free_i32(addr);
+
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index eb217af579a..0c92f3ed4ec 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3713,26 +3713,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
else
rd = VFP_SREG_D(insn);
if ((insn & 0x01200000) == 0x01000000) {
- /* Single load/store */
- offset = (insn & 0xff) << 2;
- if ((insn & (1 << 23)) == 0)
- offset = -offset;
- if (s->thumb && rn == 15) {
- /* This is actually UNPREDICTABLE */
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc & ~2);
- } else {
- addr = load_reg(s, rn);
- }
- tcg_gen_addi_i32(addr, addr, offset);
- if (insn & (1 << 20)) {
- gen_vfp_ld(s, dp, addr);
- gen_mov_vreg_F0(dp, rd);
- } else {
- gen_mov_F0_vreg(dp, rd);
- gen_vfp_st(s, dp, addr);
- }
- tcg_temp_free_i32(addr);
+ /* Already handled by decodetree */
+ return 1;
} else {
/* load/store multiple */
int w = insn & (1 << 21);
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 134f1c9ef58..8fa7fa0bead 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -71,3 +71,10 @@ VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
vm=%vm_sp
VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
vm=%vm_dp
+
+# Note that the half-precision variants of VLDR and VSTR are
+# not part of this decodetree at all because they have bits [9:8] == 0b01
+VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
+ vd=%vd_sp
+VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
+ vd=%vd_dp
--
2.20.1
- [Qemu-devel] [PULL 02/48] target/arm: Use tcg_gen_gvec_bitsel, (continued)
- [Qemu-devel] [PULL 02/48] target/arm: Use tcg_gen_gvec_bitsel, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 06/48] target/arm: Fix output of PAuth Auth, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 07/48] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 12/48] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 08/48] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 05/48] hw/core/bus.c: Only the main system bus can have no parent, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 19/48] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decodetree,
Peter Maydell <=
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 03/48] target/arm: Implement NSACR gating of floating point, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 18/48] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 28/48] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 27/48] target/arm: Convert VFP VNMLA to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 09/48] target/arm: Factor out VFP access checking code, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 25/48] target/arm: Convert VFP VMLS to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 31/48] target/arm: Convert VSUB to decodetree, Peter Maydell, 2019/06/13