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[Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register ran
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range |
Date: |
Thu, 13 Jun 2019 13:13:49 +0100 |
The SMMUv3 ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden
---
hw/arm/smmuv3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index fd8ec7860ee..e96d5beb9a8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1232,7 +1232,7 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr
offset,
uint64_t *data, MemTxAttrs attrs)
{
switch (offset) {
- case A_IDREGS ... A_IDREGS + 0x1f:
+ case A_IDREGS ... A_IDREGS + 0x2f:
*data = smmuv3_idreg(offset - A_IDREGS);
return MEMTX_OK;
case A_IDR0 ... A_IDR5:
--
2.20.1
- [Qemu-devel] [PULL 06/48] target/arm: Fix output of PAuth Auth, (continued)
- [Qemu-devel] [PULL 06/48] target/arm: Fix output of PAuth Auth, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 07/48] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 12/48] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 08/48] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 05/48] hw/core/bus.c: Only the main system bus can have no parent, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 19/48] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range,
Peter Maydell <=
- [Qemu-devel] [PULL 03/48] target/arm: Implement NSACR gating of floating point, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 18/48] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 28/48] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 27/48] target/arm: Convert VFP VNMLA to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 09/48] target/arm: Factor out VFP access checking code, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 25/48] target/arm: Convert VFP VMLS to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 31/48] target/arm: Convert VSUB to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 43/48] target/arm: Convert double-single precision conversion insns to decodetree, Peter Maydell, 2019/06/13