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[Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 V
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm |
Date: |
Mon, 17 Jun 2019 15:34:00 +0100 |
The AArch32 VMOV (immediate) instruction uses the same VFP encoded
immediate format we already handle in vfp_expand_imm(). Use that
function rather than hand-decoding it.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/translate-vfp.inc.c | 28 ++++------------------------
target/arm/vfp.decode | 10 ++++++----
2 files changed, 10 insertions(+), 28 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index a66084f6e36..8b732761f26 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1842,7 +1842,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s,
arg_VMOV_imm_sp *a)
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i32 fd;
- uint32_t n, i, vd;
+ uint32_t vd;
vd = a->vd;
@@ -1869,17 +1869,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s,
arg_VMOV_imm_sp *a)
}
}
- n = (a->imm4h << 28) & 0x80000000;
- i = ((a->imm4h << 4) & 0x70) | a->imm4l;
- if (i & 0x40) {
- i |= 0x780;
- } else {
- i |= 0x800;
- }
- n |= i << 19;
-
- fd = tcg_temp_new_i32();
- tcg_gen_movi_i32(fd, n);
+ fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
for (;;) {
neon_store_reg32(fd, vd);
@@ -1902,7 +1892,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s,
arg_VMOV_imm_dp *a)
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i64 fd;
- uint32_t n, i, vd;
+ uint32_t vd;
vd = a->vd;
@@ -1934,17 +1924,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s,
arg_VMOV_imm_dp *a)
}
}
- n = (a->imm4h << 28) & 0x80000000;
- i = ((a->imm4h << 4) & 0x70) | a->imm4l;
- if (i & 0x40) {
- i |= 0x3f80;
- } else {
- i |= 0x4000;
- }
- n |= i << 16;
-
- fd = tcg_temp_new_i64();
- tcg_gen_movi_i64(fd, ((uint64_t)n) << 32);
+ fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
for (;;) {
neon_store_reg64(fd, vd);
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index ea24365bb4c..a67b3f29ee5 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -44,6 +44,8 @@
%vmov_idx_b 21:1 5:2
%vmov_idx_h 21:1 6:1
+%vmov_imm 16:4 0:4
+
# VMOV scalar to general-purpose register; note that this does
# include some Neon cases.
VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
@@ -152,10 +154,10 @@ VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0
.... \
VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
-VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \
- vd=%vd_sp
-VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \
- vd=%vd_dp
+VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
+ vd=%vd_sp imm=%vmov_imm
+VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
+ vd=%vd_dp imm=%vmov_imm
VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \
vd=%vd_sp vm=%vm_sp
--
2.20.1
- [Qemu-devel] [PULL 07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU, (continued)
- [Qemu-devel] [PULL 07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 09/24] hw/intc/arm_gicv3: Fix decoding of ID register range, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch], Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm,
Peter Maydell <=
- [Qemu-devel] [PULL 13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US], Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 24/24] target/arm: Only implement doubles if the FPU supports them, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 23/24] target/arm: Fix typos in trans function prototypes, Peter Maydell, 2019/06/17